Puts either of two floating-point operands into the target register based on the results of comparing another floating-point operand with zero.
Note: The fsel instruction is defined only in the PowerPC architecture and is an optional instruction. It is supported on the PowerPC 603 RISC Microprocessor and the PowerPC 604 RISC Microprocessor, but not supported on the PowerPC 601 RISC Microprocessor.
| Bits | Value |
|---|---|
| 0-5 | 63 |
| 6-10 | FRT |
| 11-15 | FRA |
| 16-20 | FRB |
| 21-25 | FRC |
| 26-30 | 23 |
| 31 | Rc |
| PowerPC | |
|---|---|
| fsel | FRT, FRA, FRC, FRB |
| fsel. | FRT, FRA, FRC, FRB |
The double-precision floating-point operand in floating-point register (FPR) FRA is compared with the value zero. If the value in FRA is greater than or equal to zero, floating point register FRT is set to the contents of floating-point register FRC. If the value in FRA is less than zero or is a NaN, floating point register FRT is set to the contents of floating-point register FRB.The comparison ignores the sign of zero; both +0 and -0 are equal to zero.
The fesl instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
| Syntax Form | FPSCR bits | Record Bit (Rc) | Condition Register Field 1 |
| fsel | None | 0 | None |
| fsel. | None | 1 | FX, FEX, VX, OX |
The two syntax forms of the fsel instruction never affect the Floating-Point Status and Control Register fields. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.
Interpreting the Contents of a Floating-Point Register .