The Instruction Set Sorted by Primary and Extended Op Code table lists the instruction set, sorted first by primary op code and then by extended op code. The table column Implementation contains the following information:
Instruction Set Sorted by Primary and Extended Op Code | |||||
Mnemonic | Instruction | Implementation | Format | Primary Op Code | Extended Op Code |
ti | Trap Immediate | POWER family | D | 03 |
|
twi | Trap Word Immediate | PowerPC | D | 03 |
|
muli | Multiply Immediate | POWER family | D | 07 |
|
mulli | Multiply Low Immediate | PowerPC | D | 07 |
|
sfi | Subtract from Immediate | POWER family | D | 08 |
|
subfic | Subtract from Immediate Carrying | PowerPC | D | 08 |
|
dozi | Difference or Zero Immediate | POWER family | D | 09 |
|
cmpli | Compare Logical Immediate | com | D | 10 |
|
cmpi | Compare Immediate | com | D | 11 |
|
addic | Add Immediate Carrying | PowerPC | D | 12 |
|
ai | Add Immediate | POWER family | D | 12 |
|
si | Subtract Immediate | com | D | 12 |
|
addic. | Add Immediate Carrying and Record | PowerPC | D | 13 |
|
si. | Subtract Immediate and Record | com | D | 13 |
|
ai. | Add Immediate and Record | POWER family | D | 13 |
|
addi | Add Immediate | PowerPC | D | 14 |
|
cal | Compute Address Lower | POWER family | D | 14 |
|
addis | Add Immediate Shifted | PowerPC | D | 15 |
|
cau | Compute Address Upper | POWER family | D | 15 |
|
bc[l][a] | Branch Conditional | com | B | 16 |
|
sc | System Call | PowerPC | SC | 17 |
|
svc[l][a] | Supervisor Call | POWER family | SC | 17 |
|
b[l][a] | Branch | com | I | 18 |
|
mcrf | Move Condition Register Field | com | XL | 19 | 0 |
bclr[l] | Branch Conditional Link Register | PowerPC | XL | 19 | 16 |
bcr[l] | Branch Conditional Register | POWER family | XL | 19 | 16 |
crnor | Condition Register NOR | com | XL | 19 | 33 |
rfi | Return from Interrupt | com | X | 19 | 50 |
rfsvc | Return from SVC | POWER family | X | 19 | 82 |
crandc | Condition Register AND with Complement | com | XL | 19 | 129 |
ics | Instruction Cache Synchronize | POWER family | X | 19 | 150 |
isync | Instruction Synchronize | PowerPC | X | 19 | 150 |
crxor | Condition Register XOR | com | XL | 19 | 193 |
crnand | Condition Register NAND | com | XL | 19 | 225 |
crand | Condition Register AND | com | XL | 19 | 257 |
creqv | Condition Register Equivalent | com | XL | 19 | 289 |
crorc | Condition Register OR with Complement | com | XL | 19 | 417 |
cror | Condition Register OR | com | XL | 19 | 449 |
bcc[l] | Branch Conditional to Count Register | POWER family | XL | 19 | 528 |
bcctr[l] | Branch Conditional to Count Register | PowerPC | XL | 19 | 528 |
rlimi[.] | Rotate Left Immediate then Mask Insert | POWER family | M | 20 |
|
rlwimi[.] | Rotate Left Word Immediate then Mask Insert | PowerPC | M | 20 |
|
rlinm[.] | Rotate Left Immediate then AND with Mask | POWER family | M | 21 |
|
rlwinm[.] | Rotate Left Word Immediate then AND with Mask | PowerPC | M | 21 |
|
rlmi[.] | Rotate Left then Mask Insert | POWER family | M | 22 |
|
rlnm[.] | Rotate Left then AND with Mask | POWER family | M | 23 |
|
rlwnm[.] | Rotate Left Word then AND with Mask | PowerPC | M | 23 |
|
ori | OR Immediate | PowerPC | D | 24 |
|
oril | OR Immediate Lower | POWER family | D | 24 |
|
oris | OR Immediate Shifted | PowerPC | D | 25 |
|
oriu | OR Immediate Upper | POWER family | D | 25 |
|
xori | XOR Immediate | PowerPC | D | 26 |
|
xoril | XOR Immediate Lower | POWER family | D | 26 |
|
xoris | XOR Immediate Shift | PowerPC | D | 27 |
|
xoriu | XOR Immediate Upper | POWER family | D | 27 |
|
andi. | AND Immediate | PowerPC | D | 28 |
|
andil. | AND Immediate Lower | POWER family | D | 28 |
|
andis. | AND Immediate Shifted | PowerPC | D | 29 |
|
andiu. | AND Immediate Upper | POWER family | D | 29 |
|
cmp | Compare | com | X | 31 | 0 |
t | Trap | POWER family | X | 31 | 04 |
tw | Trap Word | PowerPC | X | 31 | 04 |
sf[o][.] | Subtract from | POWER family | XO | 31 | 08 |
subfc[o][.] | Subtract from Carrying | PowerPC | XO | 31 | 08 |
a[o][.] | Add Carrying | POWER family | XO | 31 | 10 |
addc[o][.] | Add Carrying | PowerPC | XO | 31 | 10 |
mulhwu[.] | Multiply High Word Unsigned | PowerPC | XO | 31 | 11 |
mfcr | Move from Condition Register | com | X | 31 | 19 |
lwarx | Load Word and Reserve Indexed | PowerPC | X | 31 | 20 |
lwzx | Load Word and Zero Indexed | PowerPC | X | 31 | 23 |
lx | Load Indexed | POWER family | X | 31 | 23 |
sl[.] | Shift Left | POWER family | X | 31 | 24 |
slw[.] | Shift Left Word | PowerPC | X | 31 | 24 |
cntlz[.] | Count Leading Zeros | POWER family | X | 31 | 26 |
cntlzw[.] | Count Leading Zeros Word | PowerPC | X | 31 | 26 |
and[.] | AND | com | X | 31 | 28 |
maskg[.] | Mask Generate | POWER family | X | 31 | 29 |
cmpl | Compare Logical | com | X | 31 | 32 |
subf[o][.] | Subtract from | PowerPC | XO | 31 | 40 |
dcbst | Data Cache Block Store | PowerPC | X | 31 | 54 |
lux | Load with Update Indexed | POWER family | X | 31 | 55 |
lwzux | Load Word and Zero with Update Indexed | PowerPC | X | 31 | 55 |
andc[.] | AND with Complement | com | X | 31 | 60 |
mulhw[.] | Multiply High Word | PowerPC | XO | 31 | 75 |
mfmsr | Move from Machine State Register | com | X | 31 | 83 |
dcbf | Data Cache Block Flush | PowerPC | X | 31 | 86 |
lbzx | Load Byte and Zero Indexed | com | X | 31 | 87 |
neg[o][.] | Negate | com | XO | 31 | 104 |
mul[o][.] | Multiply | POWER family | XO | 31 | 107 |
clf | Cache Line Flush | POWER family | X | 31 | 118 |
lbzux | Load Byte and Zero with Update Indexed | com | X | 31 | 119 |
nor[.] | NOR | com | X | 31 | 124 |
sfe[o][.] | Subtract from Extended | POWER family | XO | 31 | 136 |
subfe[o][.] | Subtract from Extended | PowerPC | XO | 31 | 136 |
adde[o][.] | Add Extended | PowerPC | XO | 31 | 138 |
ae[o][.] | Add Extended | POWER family | XO | 31 | 138 |
mtcrf | Move to Condition Register Fields | com | XFX | 31 | 144 |
mtmsr | Move to Machine State Register | com | X | 31 | 146 |
stwcx. | Store Word Conditional Indexed | PowerPC | X | 31 | 150 |
stwx | Store Word Indexed | PowerPC | X | 31 | 151 |
stx | Store Indexed | POWER family | X | 31 | 151 |
slq[.] | Shift Left with MQ | POWER family | X | 31 | 152 |
sle[.] | Shift Left Extended | POWER family | X | 31 | 153 |
stux | Store with Update Indexed | POWER family | X | 31 | 183 |
stwux | Store Word with Update Indexed | PowerPC | X | 31 | 183 |
sliq[.] | Shift Left Immediate with MQ | POWER family | X | 31 | 184 |
sfze[o][.] | Subtract from Zero Extended | POWER family | XO | 31 | 200 |
subfze[o][.] | Subtract from Zero Extended | PowerPC | XO | 31 | 200 |
addze[o][.] | Add to Zero Extended | PowerPC | XO | 31 | 202 |
aze[o][.] | Add to Zero Extended | POWER family | XO | 31 | 202 |
mtsr | Move to Segment Register | com | X | 31 | 210 |
stbu | Store Byte with Update | com | D | 39 | |
stbx | Store Byte Indexed | com | X | 31 | 215 |
sllq[.] | Shift Left Long with MQ | POWER family | X | 31 | 216 |
sleq[.] | Shift Left Extended with MQ | POWER family | X | 31 | 217 |
sfme[o][.] | Subtract from Minus One Extended | POWER family | XO | 31 | 232 |
subfme[o][.] | Subtract from Minus One Extended | PowerPC | XO | 31 | 232 |
addme[o][.] | Add to Minus One Extended | PowerPC | XO | 31 | 234 |
ame[o][.] | Add to Minus One Extended | POWER family | XO | 31 | 234 |
mullw[o][.] | Multiply Low Word | PowerPC | XO | 31 | 235 |
muls[o][.] | Multiply Short | POWER family | XO | 31 | 235 |
mtsri | Move to Segment Register Indirect | POWER family | X | 31 | 242 |
mtsrin | Move to Segment Register Indirect | PowerPC | X | 31 | 242 |
dcbtst | Data Cache Block Touch for Store | PowerPC | X | 31 | 246 |
stbux | Store Byte with Update Indexed | com | X | 31 | 247 |
slliq[.] | Shift Left Long Immediate with MQ | POWER family | X | 31 | 248 |
doz[o][.] | Difference or Zero | POWER family | XO | 31 | 264 |
add[o][.] | Add | PowerPC | XO | 31 | 266 |
cax[o][.] | Compute Address | POWER family | XO | 31 | 266 |
lscbx | Load String and Compare Byte Indexed | POWER family | X | 31 | 277 |
dcbt | Data Cache Block Touch | PowerPC | X | 31 | 278 |
lhzx | Load Half and Zero Indexed | com | X | 31 | 279 |
eqv[.] | Equivalent | com | X | 31 | 284 |
tlbi | Translation Look-aside Buffer Invalidate Entry | POWER family | X | 31 | 306 |
tlbie | Translation Look-aside Buffer Invalidate Entry | PPC opt. | X | 31 | 306 |
eciwx | External Control in Word Indexed | PPC opt. | X | 31 | 310 |
xor[.] | XOR | com | X | 31 | 316 |
div[o][.] | Divide | POWER family | XO | 31 | 331 |
lhzux | Load Half and Zero with Update Indexed | com | X | 31 | 331 |
mfspr | Move from Special-Purpose Register | com | X | 31 | 339 |
lhax | Load Half Algebraic Indexed | com | X | 31 | 343 |
abs[o][.] | Absolute | POWER family | XO | 31 | 360 |
divs[o][.] | Divide Short | POWER family | XO | 31 | 363 |
lhaux | Load Half Algebraic with Update Indexed | com | X | 31 | 375 |
sthx | Store Half Indexed | com | X | 31 | 407 |
orc[.] | OR with Complement | com | X | 31 | 412 |
ecowx | External Control out Word Indexed | PPC opt. | X | 31 | 438 |
sthux | Store Half with Update Indexed | com | X | 31 | 439 |
or[.] | OR | com | X | 31 | 444 |
divwu[o][.] | Divide Word Unsigned | PowerPC | XO | 31 | 459 |
mtspr | Move to Special-Purpose Register | com | X | 31 | 467 |
dcbi | Data Cache Block Invalidate | PowerPC | X | 31 | 470 |
nand[.] | NAND | com | X | 31 | 476 |
nabs[o][.] | Negative Absolute | POWER family | XO | 31 | 488 |
divw[o][.] | Divide Word | PowerPC | XO | 31 | 491 |
cli | Cache Line Invalidate | POWER family | X | 31 | 502 |
mcrxr | Move to Condition Register from XER | com | X | 31 | 512 |
clcs | Cache Line Compute Size | POWER family | X | 31 | 531 |
lswx | Load String Word Indexed | PowerPC | X | 31 | 533 |
lsx | Load String Indexed | POWER family | X | 31 | 533 |
lbrx | Load Byte-Reversed Indexed | POWER family | X | 31 | 534 |
lwbrx | Load Word Byte-Reversed Indexed | PowerPC | X | 31 | 534 |
lfsx | Load Floating-Point Single Indexed | com | X | 31 | 535 |
sr[.] | Shift Right | POWER family | X | 31 | 536 |
srw[.] | Shift Right Word | PowerPC | X | 31 | 536 |
rrib[.] | Rotate Right and Insert Bit | POWER family | X | 31 | 537 |
maskir[.] | Mask Insert from Register | POWER family | X | 31 | 541 |
tlbsync | Translation Look-aside Buffer Synchronize | PPC opt. | X | 31 | 566 |
lfsux | Load Floating-Point Single with Update Indexed | com | X | 31 | 567 |
mfsr | Move from Segment Register | com | X | 31 | 595 |
lsi | Load String Immediate | POWER family | X | 31 | 597 |
lswi | Load String Word Immediate | PowerPC | X | 31 | 597 |
dcs | Data Cache Synchronize | POWER family | X | 31 | 598 |
sync | Synchronize | PowerPC | X | 31 | 598 |
lfdx | Load Floating-Point Double Indexed | com | X | 31 | 599 |
mfsri | Move from Segment Register Indirect | POWER family | X | 31 | 627 |
dclst | Data Cache Line Store | POWER family | X | 31 | 630 |
lfdux | Load Floating-Point Double with Update Indexed | com | X | 31 | 631 |
mfsrin | Move from Segment Register Indirect | PowerPC | X | 31 | 659 |
stswx | Store String Word Indexed | PowerPC | X | 31 | 661 |
stsx | Store String Indexed | POWER family | X | 31 | 661 |
stbrx | Store Byte-Reversed Indexed | POWER family | X | 31 | 662 |
stwbrx | Store Word Byte-Reversed Indexed | PowerPC | X | 31 | 662 |
stfsx | Store Floating-Point Single Indexed | com | X | 31 | 663 |
srq[.] | Shift RIght with MQ | POWER family | X | 31 | 664 |
sre[.] | Shift Right Extended | POWER family | X | 31 | 665 |
stfsux | Store Floating-Point Single with Update Indexed | com | X | 31 | 695 |
sriq[.] | Shift Right Immediate with MQ | POWER family | X | 31 | 696 |
stsi | Store String Immediate | POWER family | X | 31 | 725 |
stswi | Store String Word Immediate | PowerPC | X | 31 | 725 |
stfdx | Store Floating-Point Double Indexed | com | X | 31 | 727 |
srlq[.] | Shift Right Long with MQ | POWER family | X | 31 | 728 |
sreq[.] | Shift Right Extended with MQ | POWER family | X | 31 | 729 |
stfdux | Store Floating-Point Double with Update Indexed | com | X | 31 | 759 |
srliq[.] | Shift Right Long Immediate with MQ | POWER family | X | 31 | 760 |
lhbrx | Load Half Byte-Reversed Indexed | com | X | 31 | 790 |
lfqx | Load Floating-Point Quad Indexed | POWER2 | X | 31 | 791 |
sra[.] | Shift Right Algebraic | POWER family | X | 31 | 792 |
sraw[.] | Shift Right Algebraic Word | PowerPC | X | 31 | 792 |
rac[.] | Real Address Compute | POWER family | X | 31 | 818 |
lfqux | Load Floating-Point Quad with Update Indexed | POWER2 | X | 31 | 823 |
srai[.] | Shift Right Algebraic Immediate | POWER family | X | 31 | 824 |
srawi[.] | Shift Right Algebraic Word Immediate | PowerPC | X | 31 | 824 |
eieio | Enforce In-order Execution of I/O | PowerPC | X | 31 | 854 |
sthbrx | Store Half Byte-Reverse Indexed | com | X | 31 | 918 |
stfqx | Store Floating-Point Quad Indexed | POWER2 | X | 31 | 919 |
sraq[.] | Shift Right Algebraic with MQ | POWER family | X | 31 | 920 |
srea[.] | Shift Right Extended Algebraic | POWER family | X | 31 | 921 |
exts[.] | Extend Sign | POWER family | X | 31 | 922 |
extsh[.] | Extend Sign Halfword | PowerPC | XO | 31 | 922 |
stfqux | Store Floating-Point Quad with Update Indexed | POWER2 | X | 31 | 951 |
sraiq[.] | Shift Right Algebraic Immediate with MQ | POWER family | X | 31 | 952 |
extsb[.] | Extend Sign Byte | PowerPC | X | 31 | 954 |
tlbld | Load Data TLB Entry | 603 only | X | 31 | 978 |
icbi | Instruction Cache Block Invalidate | PowerPC | X | 31 | 982 |
stfiwx | Store Floating-Point as Integer Word Indexed | PPC opt. | X | 31 | 983 |
tlbli | Load Instruction TLB Entry | 603 only | X | 31 | 1010 |
dcbz | Data Cache Block Set to Zero | PowerPC | X | 31 | 1014 |
dclz | Data Cache Line Set to Zero | POWER family | X | 31 | 1014 |
l | Load | POWER family | D | 32 |
|
lwz | Load Word and Zero | PowerPC | D | 32 |
|
lu | Load with Update | POWER family | D | 33 |
|
lwzu | Load Word with Zero Update | PowerPC | D | 33 |
|
lbz | Load Byte and Zero | com | D | 34 |
|
lbzu | Load Byte and Zero with Update | com | D | 35 |
|
st | Store | POWER family | D | 36 |
|
stw | Store | PowerPC | D | 36 |
|
stu | Store with Update | POWER family | D | 37 |
|
stwu | Store Word with Update | PowerPC | D | 37 |
|
stb | Store Byte | com | D | 38 |
|
lhz | Load Half and Zero | com | D | 40 |
|
lhzu | Load Half and Zero with Update | com | D | 41 |
|
lha | Load Half Algebraic | com | D | 42 |
|
lhau | Load Half Algebraic with Update | com | D | 43 |
|
sth | Store Half | com | D | 44 |
|
sthu | Store Half with Update | com | D | 45 |
|
lm | Load Multiple | POWER family | D | 46 |
|
lmw | Load Multiple Word | PowerPC | D | 46 |
|
stm | Store Multiple | POWER family | D | 47 |
|
stmw | Store Multiple Word | PowerPC | D | 47 |
|
lfs | Load Floating-Point Single | com | D | 48 |
|
lfsu | Load Floating-Point Single with Update | com | D | 49 |
|
lfd | Load Floating-Point Double | com | D | 50 |
|
lfdu | Load Floating-Point Double with Update | com | D | 51 |
|
stfs | Store Floating-Point Single | com | D | 52 |
|
stfsu | Store Floating-Point Single with Update | com | D | 53 |
|
stfd | Store Floating-Point Double | com | D | 54 |
|
stfdu | Store Floating-Point Double with Update | com | D | 55 |
|
lfq | Load Floating-Point Quad | POWER2 | D | 56 |
|
lfqu | Load Floating-Point Quad with Update | POWER2 | D | 57 |
|
fdivs[.] | Floating Divide Single | PowerPC | A | 59 | 18 |
fsubs[.] | Floating Subtract Single | PowerPC | A | 59 | 20 |
fadds[.] | Floating Add Single | PowerPC | A | 59 | 21 |
fres[.] | Floating Reciprocal Estimate Single | PPC opt. | A | 59 | 24 |
fmuls[.] | Floating Multiply Single | PowerPC | A | 59 | 25 |
fmsubs[.] | Floating Multiply-Subtract Single | PowerPC | A | 59 | 28 |
fmadds[.] | Floating Multiply-Add Single | PowerPC | A | 59 | 29 |
fnmsubs[.] | Floating Negative Multiply-Subtract Single | PowerPC | A | 59 | 30 |
fnmadds[.] | Floating Negative Multiply-Add Single | PowerPC | A | 59 | 31 |
stfq | Store Floating-Point Quad | POWER2 | DS | 60 |
|
stfqu | Store Floating-Point Quad with Update | POWER2 | DS | 61 |
|
fcmpu | Floating Compare Unordered | com | XL | 63 | 0 |
frsp[.] | Floating Round to Single Precision | com | X | 63 | 12 |
fcir[.] | Floating Convert to Integer Word | POWER family | X | 63 | 14 |
fctiw[.] | Floating Convert to Integer Word | PowerPC | X | 63 | 14 |
fcirz[.] | Floating Convert to Integer Word with Round to Zero | POWER family | X | 63 | 15 |
fctiwz[.] | Floating Convert to Integer Word with Round to Zero | PowerPC | XL | 63 | 15 |
fd[.] | Floating Divide | POWER family | A | 63 | 18 |
fdiv[.] | Floating Divide | PowerPC | A | 63 | 18 |
fs[.] | Floating Subtract | POWER family | A | 63 | 20 |
fsub[.] | Floating Subtract | PowerPC | A | 63 | 20 |
fa[.] | Floating Add | POWER family | A | 63 | 21 |
fadd[.] | Floating Add | PowerPC | A | 63 | 21 |
fsqrt[.] | Floating Square Root | POWER2 | A | 63 | 22 |
fsel[.] | Floating-Point Select | PPC opt. | A | 63 | 23 |
fm[.] | Floating Multiply | POWER family | A | 63 | 25 |
fmul[.] | Floating Multiply | PowerPC | A | 63 | 25 |
frsqrte[.] | Floating Reciprocal Square Root Estimate | PPC opt. | A | 63 | 26 |
fms[.] | Floating Multiply-Subtract | POWER family | A | 63 | 28 |
fmsub[.] | Floating Multiply-Subtract | PowerPC | A | 63 | 28 |
fma[.] | Floating Multiply-Add | POWER family | A | 63 | 29 |
fmadd[.] | Floating Multiply-Add | PowerPC | A | 63 | 29 |
fnms[.] | Floating Negative Multiply-Subtract | POWER family | A | 63 | 30 |
fnmsub[.] | Floating Negative Multiply-Subtract | PowerPC | A | 63 | 30 |
fnma[.] | Floating Negative Multiply-Add | POWER family | A | 63 | 31 |
fnmadd[.] | Floating Negative Multiply-Add | PowerPC | A | 63 | 31 |
fcmpo | Floating Compare Ordered | com | X | 63 | 32 |
mtfsb1[.] | Move to FPSCR Bit 1 | com | X | 63 | 38 |
fneg[.] | Floating Negate | com | X | 63 | 40 |
mcrfs | Move to Condition Register from FPSCR | com | X | 63 | 64 |
mtfsb0[.] | Move to FPSCR Bit 0 | com | X | 63 | 70 |
fmr[.] | Floating Move Register | com | X | 63 | 72 |
mtfsfi[.] | Move to FPSCR Field Immediate | com | X | 63 | 134 |
fnabs[.] | Floating Negative Absolute Value | com | X | 63 | 136 |
fabs[.] | Floating Absolute Value | com | X | 63 | 264 |
mffs[.] | Move from FPSCR | com | X | 63 | 583 |
mtfsf[.] | Move to FPSCR Fields | com | XFL | 63 | 711 |