Assembler Language Reference

adde or ae (Add Extended) Instruction

Purpose

Adds the contents of two general-purpose registers to the value of the Carry bit in the Fixed-Point Exception Register and places the result in a general-purpose register.

Syntax

Bits	Value
0-5	31
6-10	RT
11-15	RA
16-20	RB
21	OE
22-30	138
31	Rc

PowerPC
adde	RT, RA, RB
adde.	RT, RA, RB
addeo	RT, RA, RB
addeo.	RT, RA, RB

POWER family
ae	RT, RA, RB
ae.	RT, RA, RB
aeo	RT, RA, RB
aeo.	RT, RA, RB

Description

The adde and ae instructions place the sum of the contents of general-purpose register (GPR) RA, GPR RB, and the Carry bit into the target GPR RT.

The adde instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The ae instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
adde	0	CA	0	None
adde.	0	CA	1	LT,GT,EQ,SO
addeo	1	SO,OV,CA	0	None
addeo.	1	SO,OV,CA	1	LT,GT,EQ,SO
ae	0	CA	0	None
ae.	0	CA	1	LT,GT,EQ,SO
aeo	1	SO,OV,CA	0	None
aeo.	1	SO,OV,CA	1	LT,GT,EQ,SO

The four syntax forms of the adde instruction and the four syntax forms of the ae instruction always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction affects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RT	Specifies target general-purpose register where result of operation is stored.
RA	Specifies source general-purpose register for operation.
RB	Specifies source general-purpose register for operation.

Examples

The following code adds the contents of GPR 4, the contents of GPR 10, and the Fixed-Point Exception Register Carry bit and stores the result in GPR 6:

# Assume GPR 4 contains 0x1000 0400.
# Assume GPR 10 contains 0x1000 0400.
# Assume the Carry bit is one.
adde 6,4,10
# GPR 6 now contains 0x2000 0801.

The following code adds the contents of GPR 4, the contents of GPR 10, and the Fixed-Point Exception Register Carry bit; stores the result in GPR 6; and sets Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0x9000 3000.
# Assume GPR 10 contains 0x7B41 92C0.
# Assume the Carry bit is zero.
adde. 6,4,10
# GPR 6 now contains 0x0B41 C2C0.
```

The following code adds the contents of GPR 4, the contents of GPR 10, and the Fixed-Point Exception Register Carry bit; stores the result in GPR 6; and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0x1000 0400.
# Assume GPR 10 contains 0xEFFF FFFF.
# Assume the Carry bit is one.
addeo 6,4,10
# GPR 6 now contains 0x0000 0400.
```

The following code adds the contents of GPR 4, the contents of GPR 10, and the Fixed-Point Exception Register Carry bit; stores the result in GPR 6; and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0x9000 3000.
# Assume GPR 10 contains 0x8000 7000.
# Assume the Carry bit is zero.
addeo. 6,4,10
# GPR 6 now contains 0x1000 A000.
```

Related Information

Fixed-Point Processor .

Fixed-Point Arithmetic Instructions .