Assembler Language Reference

add (Add) or cax (Compute Address) Instruction

Purpose

Adds the contents of two general-purpose registers.

Syntax

Bits	Value
0-5	31
6-10	RT
11-15	RA
16-20	RB
21	OE
22-30	266
31	Rc

PowerPC
add	RT, RA, RB
add.	RT, RA, RB
addo	RT, RA, RB
addo.	RT, RA, RB

POWER family
cax	RT, RA, RB
cax.	RT, RA, RB
caxo	RT, RA, RB
caxo.	RT, RA, RB

Description

The add and cax instructions place the sum of the contents of general-purpose register (GPR) RA and GPR RB into the target GPR RT.

The add and cax instructions have four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
add	0	None	0	None
add.	0	None	1	LT,GT,EQ,SO
addo	1	SO,OV	0	None
addo.	1	SO,OV	1	LT,GT,EQ,SO
cax	0	None	0	None
cax.	0	None	1	LT,GT,EQ,SO
caxo	1	SO,OV	0	None
caxo.	1	SO,OV	1	LT,GT,EQ,SO

The four syntax forms of the add instruction and the four syntax forms of the cax instruction never affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction affects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RT	Specifies target general-purpose register where result of operation is stored.
RA	Specifies source general-purpose register for operation.
RB	Specifies source general-purpose register for operation.

Examples

The following code adds the address or contents in GPR 6 to the address or contents in GPR 3 and stores the result in GPR 4:
```
# Assume GPR 6 contains 0x0004 0000.
# Assume GPR 3 contains 0x0000 4000.
add 4,6,3
# GPR 4 now contains 0x0004 4000.
```

The following code adds the address or contents in GPR 6 to the address or contents in GPR 3, stores the result in GPR 4, and sets Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 6 contains 0x8000 7000.
# Assume GPR 3 contains 0x7000 8000.
 add. 4,6,3
# GPR 4 now contains 0xF000 F000.
```

The following code adds the address or contents in GPR 6 to the address or contents in GPR 3, stores the result in GPR 4, and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 6 contains 0xEFFF FFFF.
# Assume GPR 3 contains 0x8000 0000.
addo 4,6,3
# GPR 4 now contains 0x6FFF FFFF.
```

The following code adds the address or contents in GPR 6 to the address or contents in GPR 3, stores the result in GPR 4, and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 6 contains 0xEFFF FFFF.
# Assume GPR 3 contains 0xEFFF FFFF.
addo. 4,6,3
# GPR 4 now contains 0xDFFF FFFE.
```

Related Information

Fixed-Point Processor .

Fixed-Point Address Computation Instructions .