Rotates the contents of a general-purpose register to the left by a specified number of bits and places the masked result in a general-purpose register.
The srw and sr instructions rotate the contents of the source general-purpose register (GPR) RS to the left by 32 minus N bits, where N is the shift amount specified in bits 27-31 of GPR RB, and store the logical AND of the rotated word and the generated mask in GPR RA.
Consider the following when using the srw and sr instructions:
The srw and sr instruction each have two syntax forms. Each syntax form has a different effect on Condition Register Field 0.
|Syntax Form||Overflow Exception (OE)||Fixed-Point Exception Register||Record Bit (Rc)||Condition Register Field 0|
The two syntax forms of the sr instruction, and the two syntax forms of the srw instruction, never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, these instructions affect the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.
|RA||Specifies target general-purpose register where result of operation is stored.|
|RS||Specifies source general-purpose register for operation.|
|RB||Specifies source general-purpose register for operation.|
# Assume GPR 4 contains 0x9000 3000. # Assume GPR 5 contains 0x0000 0024. srw 6,4,5 # GPR 6 now contains 0x0000 0000.
# Assume GPR 4 contains 0xB004 3001. # Assume GPR 5 contains 0x0000 0004. srw. 6,4,5 # GPR 6 now contains 0x0B00 4300. # Condition Register Field 0 now contains 0x4.
The addze or aze (Add to Zero Extended) instruction.
Fixed-Point Rotate and Shift Instructions.