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AIX Version 4.3 Assembler Language Reference

addze or aze (Add to Zero Extended) Instruction

Purpose

Adds the contents of a general-purpose register, zero, and the value of the Carry bit in the FIxed-Point Exception Register and places the result in a general-purpose register.

Syntax

PowerPC
addze RT,RA
addze. RT,RA
addzeo RT,RA
addzeo. RT,RA
POWER
aze RT,RA
aze. RT,RA
azeo RT,RA
azeo. RT,RA

Description

The addze and aze instructions add the contents of general-purpose register (GPR) RA, the Carry bit, and 0x0000 0000 and place the result into the target GPR RT.

The addze instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The aze instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

Syntax Form Overflow Exception (OE) Fixed-Point Exception Register Record Bit (Rc) Condition Register Field 0
addze 0 CA 0 None
addze. 0 CA 1 LT,GT,EQ,SO
addzeo 1 SO,OV,CA 0 None
addzeo. 1 SO,OV,CA 1 LT,GT,EQ,SO
aze 0 CA 0 None
aze. 0 CA 1 LT,GT,EQ,SO
azeo 1 SO,OV,CA 0 None
azeo. 1 SO,OV,CA 1 LT,GT,EQ,SO

The four syntax forms of the addze instruction and the four syntax forms of the aze instruction always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction affects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RT Specifies target general-purpose register where result of operation is stored.
RA Specifies source general-purpose register for operation.

Examples

  1. The following code adds the contents of GPR 4, 0, and the Carry bit and stores the result in GPR 6: 
    # Assume GPR 4 contains 0x7B41 92C0.
# Assume the Carry bit is zero.
addze 6,4
# GPR 6 now contains 0x7B41 92C0.
  2. The following code adds the contents of GPR 4, 0, and the Carry bit, stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation: 
    # Assume GPR 4 contains 0xEFFF FFFF.
# Assume the Carry bit is one.
addze. 6,4
# GPR 6 now contains 0xF000 0000.
  3. The following code adds the contents of GPR 4, 0, and the Carry bit; stores the result in GPR 6; and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register to reflect the result of the operation: 
    # Assume GPR 4 contains 0x9000 3000.
# Assume the Carry bit is one.
addzeo 6,4
# GPR 6 now contains 0x9000 3001.
  4. The following code adds the contents of GPR 4, 0, and the Carry bit; stores the result in GPR 6; and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation: 
    # Assume GPR 4 contains 0xEFFF FFFF.
# Assume the Carry bit is zero.
adzeo. 6,4
# GPR 6 now contains 0xEFFF FFFF.

Related Information

Fixed-Point Processor.

Fixed-Point Arithmetic Instructions.

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