Generates a mask of ones and zeros and loads it into a general-purpose register.
Note: The maskg instruction is supported only in the POWER architecture.
POWER | |
---|---|
maskg | RA,RS,RB |
maskg. | RA,RS,RB |
The maskg instruction generates a mask from a starting point defined by bits 27-31 of general-purpose register (GPR) RS to an end point defined by bits 27-31 of GPR RB and stores the mask in GPR RA.
Consider the following when using the maskg instruction:
The maskg instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.
Syntax Form | Overflow Exception (OE) | Fixed-Point Exception Register | Record Bit (Rc) | Condition Register Field 0 |
maskg | None | None | 0 | None |
maskg. | None | None | 1 | LT,GT,EQ,SO |
The two syntax forms of the maskg instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.
# Assume GPR 4 contains 0x0000 0014. # Assume GPR 5 contains 0x0000 0010. maskg 6,5,4 # GPR 6 now contains 0x0000 F800.
# Assume GPR 4 contains 0x0000 0010. # Assume GPR 5 contains 0x0000 0017. # Assume CR = 0. maskg. 6,5,4 # GPR 6 now contains 0xFFFF 81FF. # CR now contains 0x8000 0000.
Fixed-Point Rotate and Shift Instructions.