Compares the contents of two floating-point registers.
The fcmpu instruction compares the 64-bit double precision floating-point operand in floating-point register (FPR) FRA to the 64-bit double precision floating-point operand in FPR FRB. The Floating-Point Condition Code Field (FPCC) of the Floating-Point Status and Control Register (FPSCR) is set to reflect the value of the operand FRA with respect to operand FRB. The value BF determines which field in the condition register receives the four FPCC bits.
Consider the following when using the fcmpu instruction:
The fcmpu instruction has one syntax form and always affects the FT, FG, FE, FU, and VXSNAN bits in the FPSCR.
|BF||Specifies a field in the condition register that receives the four FPCC bits.|
|FRA||Specifies source floating-point register.|
|FRB||Specifies source floating-point register.|
The following code compares the contents of FPR 5 and FPR 4:
# Assume FPR 5 holds 0xC053 4000 0000 0000. # Assume FPR 4 holds 0x400C 0000 0000 0000. # Assume CR = 0 and FPSCR = 0. fcmpu 6,4,5 # CR now contains 0x0000 0040. # FPSCR now contains 0x0000 4000.
Floating-Point Compare Instructions.