fcmpo (Floating Compare Ordered) Instruction

Purpose

Compares the contents of two floating-point registers.

Syntax

Description

The fcmpo instruction compares the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRA to the 64-bit, double-precision floating-point operand in FPR FRB. The Floating-Point Condition Code Field (FPCC) of the Floating-Point Status and Control Register (FPSCR) is set to reflect the value of the operand FPR FRA with respect to operand FPR FRB. The value BF determines which field in the condition register receives the four FPCC bits.

Consider the following when using the fcmpo instruction:

• If one of the operands is either a Quiet NaN (QNaN) or a Signaling NaN (SNaN), the Floating-Point Condition Code is set to reflect unordered (FU).
• If one of the operands is a SNaN, then the Floating-Point Invalid Operation Exception bit VXSNAN of the Floating-Point Status and Control Register is set. Also:
  • If Invalid Operation is disabled (that is, the Floating-Point Invalid Operation Exception Enable bit of the Floating-Point Status and Control Register is 0), then the Floating-Point Invalid Operation Exception bit VXVC is set (signaling an an invalid compare).
  • If one of the operands is a QNaN, then the Floating-Point Invalid Operation Exception bit VXVC is set.

The fcmpo instruction has one syntax form and always affects the FT, FG, FE, FU, VXSNAN, and VXVC bits in the Floating-Point Status and Control Register.

Parameters

Examples

The following code compares the contents of FPR 4 and FPR 6 and sets Condition Register Field 1 and the Floating-Point Status and Control Register to reflect the result of the operation:

# Assume CR = 0 and FPSCR = 0.
# Assume FPR 5 contains 0xC053 4000 0000 0000. 
# Assume FPR 4 contains 0x400C 0000 0000 0000.
fcmpo 6,4,5
# CR now contains 0x0000 0040.
# FPSCR now contains 0x0000 4000.

Related Information

Floating-Point Processor.

Floating-Point Compare Instructions.