Convert the contents of a floating-point register to a 64-bit signed fixed-point integer, placing the results into another floating-point register.
|fctid||FRT, FRB (Rc=0)|
|fctid.||FRT, FRB (Rc=1)|
The floating-point operand in floating-point register (FPR) FRB is converted to a 64-bit signed fixed-point integer, using the rounding mode specified by FPSCR[RN], and placed into FPR FRT.
If the operand in FRB is greater than 2**63 - 1, then FPR FRT is set to 0x7FFF_FFFF_FFFF_FFFF. If the operand in FRB is less than 2**63 , then FPR FRT is set to 0x8000_0000_0000_0000.
Except for enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact.The fctid instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
|Syntax Form||Floating-Point Status and Control Register||Record Bit (Rc)||Condition Register Field 1|
|FRT||Specifies the target floating-point register for the operation.|
|FRB||Specifies the source floating-point register for the operation.|
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.