divwu (Divide Word Unsigned) Instruction

Purpose

Divides the contents of a general-purpose register by the contents of another general-purpose register and stores the result in a third general-purpose register.

Note: The divwu instruction is supported only in the PowerPC architecture.

Syntax

Description

The divwu instruction divides the contents of general-purpose register (GPR) RA by the contents of GPR RB, and stores the result in the target GPR RT. The dividend, divisor, and quotient are interpreted as unsigned integers.

For the case of division by 0, the content of GPR RT is undefined.

Note: Although the operation treats the result as an unsigned integer, if Rc is 1, the Less Than (LT) zero, Greater Than (GT) zero, and Equal To (EQ) zero bits of Condition Register Field 0 are set as if the result were interpreted as a signed integer.

The divwu instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The four syntax forms of the divwu instruction never affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction affects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

Examples

1. The following code divides the contents of GPR 4 by the contents of GPR 6 and stores the result in GPR 4:

   # Assume GPR 4 contains 0x0000 0000.
   # Assume GPR 6 contains 0x0000 0002.
   divwu 4,4,6
   # GPR 4 now contains 0x0000 0000.

2. The following code divides the contents of GPR 4 by the contents of GPR 6, stores the result in GPR 4 and sets Condition Register Field 0 to reflect the result of the operation:

   # Assume GPR 4 contains 0x0000 0002.
   # Assume GPR 6 contains 0x0000 0002.
   divwu. 4,4,6
   # GPR 4 now contains 0x0000 0001.

3. The following code divides the contents of GPR 4 by the contents of GPR 6, places the result in GPR 4, and sets the Summary Overflow and Overflow bits in the Fixed-Point Exception Register to reflect the result of the operation:

   # Assume GPR 4 contains 0x0000 0001.
   # Assume GPR 6 contains 0x0000 0000.
   divwuo 4,4,6
   # GPR 4 now contains an undefined quantity.

4. The following code divides the contents of GPR 4 by the contents of GPR 6, places the result in GPR 4, and sets the Summary Overflow and Overflow bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:

   # Assume GPR 4 contains 0x8000 0000.
   # Assume GPR 6 contains 0x0000 0002.
   divwuo. 4,4,6
   # GPR 4 now contains 0x4000 0000.

Related Information

Fixed-Point Processor.

Fixed-Point Arithmetic Instructions.