Divides the contents of a general-purpose register by the contents of another general-purpose register and stores the result in a third general-purpose register.
Note: The divw instruction is supported only in the PowerPC architecture.
The divw instruction divides the contents of general-purpose register (GPR) RA by the contents of GPR RB, and stores the result in the target GPR RT. The dividend, divisor, and quotient are interpreted as signed integers.
For the case of -2**31 -1, and all other cases that cause overflow, the content of GPR RT is undefined.
The divw instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.
|Syntax Form||Overflow Exception (OE)||Fixed-Point Exception Register||Record Bit (Rc)||Condition Register Field 0|
The four syntax forms of the divw instruction never affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction affects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.
|RT||Specifies target general-purpose register where result of operation is stored.|
|RA||Specifies source general-purpose register for dividend.|
|RB||Specifies source general-purpose register for divisor.|
# Assume GPR 4 contains 0x0000 0000. # Assume GPR 6 contains 0x0000 0002. divw 4,4,6 # GPR 4 now contains 0x0000 0000.
# Assume GPR 4 contains 0x0000 0002. # Assume GPR 6 contains 0x0000 0002. divw. 4,4,6 # GPR 4 now contains 0x0000 0001.
# Assume GPR 4 contains 0x0000 0001. # Assume GPR 6 contains 0x0000 0000. divwo 4,4,6 # GPR 4 now contains an undefined quantity.
# Assume GPR 4 contains 0x8000 0000. # Assume GPR 6 contains 0xFFFF FFFF. divwo. 4,4,6 # GPR 4 now contains undefined quantity.
Fixed-Point Arithmetic Instructions.