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AIX Version 4.3 Assembler Language Reference

addis or cau (Add Immediate Shifted) Instruction


Calculates an address from a concatenated offset and a base address and loads the result in a general-purpose register.


addis RT,RA,SI
cau RT,RA,UI

See "Extended Mnemonics of Fixed-Point Arithmetic Instructions" and "Extended Mnemonics of Fixed-Point Load Instructions" for more information.


The addis and cau instructions place the sum of the contents of general-purpose register (GPR) RA and the concatenation of a 16-bit unsigned integer, SI or UI, and x'0000' into the target GPR RT. If GPR RA is GPR 0, then the sum of the concatenation of 0, SI or UI, and x'0000' is stored into the target GPR RT.

The addis and cau instructions have one syntax form and do not affect Condition Register Field 0 or the Fixed-Point Exception Register.

Note: The immediate value for the cau instruction is a 16-bit unsigned integer, whereas the immediate value for the addis instruction is a 16-bit signed integer. This difference is a result of extending the architecture to 64 bits.

The assembler does a 0 to 65535 value-range check for the UI field, and a -32768 to 32767 value-range check for the SI field.

To keep the source compatibility of the addis and cau instructions, the assembler expands the value-range check for the addis instruction to -65536 to 65535. The sign bit is ignored and the assembler only ensures that the immediate value fits into 16 bits. This expansion does not affect the behavior of a 32-bit implementation or 32-bit mode in a 64-bit implementation.

The addis instruction has different semantics in 32-bit mode than it does in 64-bit mode. If bit 32 is set, it propagates through the upper 32 bits of the 64-bit general-purpose register. Use caution when using the addis instruction to construct an unsigned integer. The addis instruction with an unsigned integer in 32-bit may not be directly ported to 64-bit mode. The code sequence needed to construct an unsigned integer in 64-bit mode is significantly different from that needed in 32-bit mode.


RT Specifies target general-purpose register where result of operation is stored.
RA Specifies first source general-purpose register for operation.
UI Specifies 16-bit unsigned integer for operation.
SI Specifies
16-bit signed integer for operation.


The following code adds an offset of 0x0011 0000 to the address or contents contained in GPR 6 and loads the result into GPR 7:

# Assume GPR 6 contains 0x0000 4000.
addis 7,6,0x0011
# GPR 7 now contains 0x0011 4000.

Related Information

Fixed-Point Processor.

Fixed-Point Address Computation Instructions.

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