Ensures that a tlbie and tlbia instruction executed by one processor has completed on all other processors.
Note: The tlbsync instruction is defined only in the PowerPC architecture and is an optional instruction. It is supported on the PowerPC 603 RISC Microprocessor and on the PowerPC 604 RISC Microprocessor, but not on the PowerPC 601 RISC Microprocessor.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | /// |
| 11-15 | /// |
| 16-20 | /// |
| 21-30 | 566 |
| 31 | / |
PowerPC
tlbsync
The tlbsync instruction does not complete until all previous tlbie and tlbia instructions executed by the processor executing the tlbsync instruction have been received and completed by all other processors.
The tlbsync instruction has one syntax form and does not affect the Fixed-Point Exception Register. If the Record bit (Rc) is set to 1, the instruction form is invalid.
The tlbsync instruction is privileged.