Assembler Language Reference

subfe or sfe (Subtract from Extended) Instruction

Purpose

Adds the one's complement of the contents of a general-purpose register to the sum of another general-purpose register and then adds the value of the Fixed-Point Exception Register Carry bit and stores the result in a third general-purpose register.

Syntax

Bits	Value
0-5	31
6-10	RT
11-15	RA
16-20	RB
21	OE
22-30	136
31	Rc

PowerPC
subfe	RT, RA, RB
subfe.	RT, RA, RB
subfeo	RT, RA, RB
subfeo.	RT, RA, RB

POWER family
sfe	RT, RA, RB
sfe.	RT, RA, RB
sfeo	RT, RA, RB
sfeo.	RT, RA, RB

Description

The subfe and sfe instructions add the value of the Fixed-Point Exception Register Carry bit, the contents of general-purpose register (GPR) RB, and the one's complement of the contents of GPR RA and store the result in the target GPR RT.

The subfe instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The sfe instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
subfe	0	CA	0	None
subfe.	0	CA	1	LT,GT,EQ,SO
subfeo	1	SO,OV,CA	0	None
subfeo.	1	SO,OV,CA	1	LT,GT,EQ,SO
sfe	0	CA	0	None
sfe.	0	CA	1	LT,GT,EQ,SO
sfeo	1	SO,OV,CA	0	None
sfeo.	1	SO,OV,CA	1	LT,GT,EQ,SO

The four syntax forms of the subfe instruction, and the four syntax forms of the sfe instruction, always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction affects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RT	Specifies target general-purpose register where result of operation is stored.
RA	Specifies source general-purpose register for operation.
RB	Specifies source general-purpose register for operation.

Examples

The following code adds the one's complement of the contents of GPR 4, the contents of GPR 10, and the value of the Fixed-Point Exception Register Carry bit and stores the result in GPR 6:
```
# Assume GPR 4 contains 0x9000 3000.
# Assume GPR 10 contains 0x8000 7000.
# Assume the Carry bit is one.
subfe 6,4,10
# GPR 6 now contains 0xF000 4000.
```

The following code adds the one's complement of the contents of GPR 4, the contents of GPR 10, and the value of the Fixed-Point Exception Register Carry bit, stores the result in GPR 6, and sets Condition Register field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0x0000 4500.
# Assume GPR 10 contains 0x8000 7000.
# Assume the Carry bit is zero.
subfe. 6,4,10
# GPR 6 now contains 0x8000 2AFF.
```

The following code adds the one's complement of the contents of GPR 4, the contents of GPR 10, and the value of the Fixed-Point Exception Register Carry bit, stores the result in GPR 6, and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0x8000 0000.
# Assume GPR 10 contains 0xEFFF FFFF.
# Assume the Carry bit is one.
subfeo 6,4,10
# GPR 6 now contains 0x6FFF FFFF.
```

The following code adds the one's complement of the contents of GPR 4, the contents of GPR 10, and the value of the Fixed-Point Exception Register Carry bit, stores the result in GPR 6, and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0x8000 0000.
# Assume GPR 10 contains 0xEFFF FFFF.
# Assume the Carry bit is zero.
subfeo. 6,4,10
# GPR 6 now contains 0x6FFF FFFE.
```

Related Information

Fixed-Point Processor .

Fixed-Point Arithmetic Instructions .