Assembler Language Reference

stfqux (Store Floating-Point Quad with Update Indexed) Instruction

Purpose

Stores in memory two double-precision values at two consecutive doubleword locations and updates the address base.

Note: The stfqux instruction is supported only in the POWER2 implementation of the POWER family architecture.

Syntax

Bits	Value
0-5	31
6-10	FRS
11-15	RA
16-20	RB
21-30	951
31	Rc

POWER2
stfqux	FRS, RA, RB

Description

The stfqux instruction stores in memory the contents of two consecutive floating-point registers (FPR) at the location specified by the effective address (EA).

If general-purpose register (GPR) RA is not 0, the EA is the sum of the contents of GPR RA and GPR RB. If GPR RA is 0, the EA is the contents of GPR RB. The contents of FPR FRS is stored into the doubleword of storage at the EA. If FPR FRS is 31, then the contents of FPR 0 is stored into the doubleword at EA+8; otherwise, the contents of FRS+1 is stored into the doubleword at EA+8.

If GPR RA is not 0, the EA is placed into GPR RA.

The stfqux instruction has one syntax form and does not affect the Floating-Point Status and Control Register or Condition Register Field 0.

Parameters

FRS	Specifies the first of two floating-point registers that contain the values to be stored.
RA	Specifies the first source general-purpose register for the EA calculation and the target register for the EA update.
RB	Specifies the second source general-purpose register for the EA calculation.

Related Information

The lfqux (Load Floating-Point Quad with Update Indexed) instruction.

Floating-Point Processor .

Floating-Point Load and Store Instructions .