Assembler Language Reference

srawi or srai (Shift Right Algebraic Word Immediate) Instruction

Purpose

Rotates the contents of a general-purpose register a specified number of bits to the left, merges the rotated data with a word of 32 sign bits from that register under control of a generated mask, and places the result in another general-purpose register.

Syntax

Bits	Value
0-5	31
6-10	RS
11-15	RA
16-20	SH
21-30	824
31	Rc

PowerPC
srawi	RA, RS, SH
srawi.	RA, RS, SH

POWER family
srai	RA, RS, SH
srai.	RA, RS, SH

Description

The srawi and srai instructions rotate the contents of the source general-purpose register (GPR) RS to the left by 32 minus N bits, where N is the shift amount specified by SH, merge the rotated data with a word of 32 sign bits from GPR RS under control of a generated mask, and store the merged result in GPR RA. A word of 32 sign bits is generated by taking the sign bit of a GPR and repeating it 32 times to make a full word. This word can be either 0x0000 0000 or 0xFFFF FFFF depending on the value of the GPR. The mask consists of N zeros followed by 32 minus N ones.

The srawi and srai instructions then AND the rotated data with the complement of the generated mask, OR the 32-bit result together, and AND the bit result with bit 0 of GPR RS to produce the Carry bit (CA).

The srawi and srai instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
srawi	None	CA	0	None
srawi.	None	CA	1	LT,GT,EQ,SO
srai	None	CA	0	None
srai.	None	CA	1	LT,GT,EQ,SO

The two syntax forms of the srawi instruction, and the two syntax forms of the srai instruction, always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instructions affect the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA	Specifies target general-purpose register where result of operation is stored.
RS	Specifies source general-purpose register for operation.
SH	Specifies immediate value for shift amount.

Examples

The following code rotates the contents of GPR 4 to the left by 28 bits, merges the result with 32 sign bits under control of a generated mask, stores the result in GPR 6, and sets the Carry bit in the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0x9000 3000.
srawi 6,4,0x4
# GPR 6 now contains 0xF900 0300.
```

The following code rotates the contents of GPR 4 to the left by 28 bits, merges the result with 32 sign bits under control of a generated mask, places the result in GPR 6, and sets the Carry bit in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0xB004 3000.
srawi. 6,4,0x4
# GPR 6 now contains 0xFB00 4300.
# Condition Register Field 0 now contains 0x8.
```

Related Information

The addze or aze (Add to Zero Extended) instruction.

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .