Assembler Language Reference

sraq (Shift Right Algebraic with MQ) Instruction

Purpose

Rotates a general-purpose register a specified number of bits to the left, merges the result with a word of 32 sign bits from that general-purpose register under control of a generated mask, and places the rotated word in the MQ Register and the merged result in another general-purpose register.

Note: The sraq instruction is supported only in the POWER family architecture.

Syntax

Description

The sraq instruction rotates the contents of the source general-purpose register (GPR) RS to the left by 32 minus N bits, where N is the shift amount specified in bits 27-31 of GPR RB. The instruction then merges the rotated data with a word of 32 sign bits from GPR RS under control of a generated mask and stores the merged word in GPR RA. The rotated word is stored in the MQ Register. The mask depends on the value of bit 26 in GPR RB.

Consider the following when using the sraq instruction:

• If bit 26 of GPR RB is 0, then a mask of N zeros followed by 32 minus N ones is generated.
• If bit 26 of GPR RB is 1, then a mask of all zeros is generated.

A word of 32 sign bits is generated by taking the sign bit of a GPR and repeating it 32 times to make a full word. This word can be either 0x0000 0000 or 0xFFFF FFFF depending on the value of the GPR.

This instruction then ANDs the rotated data with the complement of the generated mask, ORs the 32-bit result together, and ANDs the bit result with bit 0 of GPR RS to produce the Carry bit (CA).

The sraq instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

The two syntax forms of the sraq instruction always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

Examples

1. The following code rotates the contents of GPR 4 to the left by 28 bits, merges the result with 32 sign bits under control of a generated mask, places the result in GPR 6 and the rotated word in the MQ Register, and sets the Carry bit in the Fixed-Point Exception Register to reflect the result of the operation:

   # Assume GPR 4 contains 0x9000 3000.
   # Assume GPR 7 contains 0x0000 0024.
   sraq 6,4,7
   # GPR 6 now contains 0xFFFF FFFF.
   # The MQ Register now contains 0x0900 0300.

2. The following code rotates the contents of GPR 4 to the left by 28 bits, merges the result with 32 sign bits under control of a generated mask, places the result in GPR 6 and the rotated word in the MQ Register, and sets the Carry bit in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:

   # Assume GPR 4 contains 0xB004 3000.
   # Assume GPR 7 contains 0x0000 0004.
   sraq. 6,4,7
   # GPR 6 now contains 0xFB00 4300.
   # The MQ Register now contains 0x0B00 4300.
   # Condition Register Field 0 now contains 0x4.

Related Information

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .