Assembler Language Reference

sllq (Shift Left Long with MQ) Instruction

Purpose

Rotates the contents of a general-purpose register to the left by the number of bits specified in a general-purpose register, merges either the rotated data or a word of zeros with the contents of the MQ Register, and places the result in a third general-purpose register.

Note: The sliq instruction is supported only in the POWER family architecture.

Syntax

Bits	Value
0-5	31
6-10	RS
11-15	RA
16-20	RB
21-30	216
31	Rc

POWER family
sllq	RA, RS, RB
sllq.	RA, RS, RB

Description

The sllq instruction rotates the contents of the source general-purpose register (GPR) RS to the left by N bits, where N is the shift amount specified in bits 27-31 of GPR RB. The merge depends on the value of bit 26 in GPR RB.

Consider the following when using the sllq instruction:

If bit 26 of GPR RB is 0, then a mask of N zeros followed by 32 minus N ones is generated. The rotated word is then merged with the contents of the MQ Register under the control of this generated mask.

If bit 26 of GPR RB is 1, then a mask of N ones followed by 32 minus N zeros is generated. A word of zeros is then merged with the contents of the MQ Register under the control of this generated mask.

The resulting merged word is stored in GPR RA. The MQ Register is not altered.

The sllq instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
sllq	None	None	0	None
sllq.	None	None	1	LT,GT,EQ,SO

The two syntax forms of the sllq instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA	Specifies target general-purpose register where result of operation is stored.
RS	Specifies source general-purpose register for operation.
RB	Specifies source general-purpose register for operation.

Examples

The following code rotates the contents of GPR 4 to the left by 4 bits, merges a word of zeros with the contents of the MQ Register under a mask, and places the merged result in GPR 6:

# Assume GPR 4 contains 0x9000 3000.
# Assume GPR 5 contains 0x0000 0024.
# Assume MQ Register contains 0xABCD EFAB.
sllq 6,4,5
# GPR 6 now contains 0xABCD EFA0.
# The MQ Register remains unchanged.

The following code rotates the contents of GPR 4 to the left by 4 bits, merges the rotated data with the contents of the MQ Register under a mask, places the merged result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0xB004 3000.
# Assume GPR 5 contains 0x0000 0004.
# Assume MQ Register contains 0xFFFF FFFF.
sllq. 6,4,5
# GPR 6 now contains 0x0043 000F.
# The MQ Register remains unchanged.
# Condition Register Field 0 now contains 0x4.
```

Related Information

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .