Assembler Language Reference

mulhdu (Multiply High Double Word Unsigned) Instruction

Purpose

Multiply 2 unsigned 64-bit values together. Place the high-order 64 bits of the result into a register.

Syntax

Bits	Value
0-5	31
6-10	D
11-15	A
16-20	B
21	0
22-30	9
31	Rc

POWER family
mulhdu	RT, RA, RB (Rc=0)
mulhdu.	RT, RA, RB (Rc=1)

Description

Both the operands and the product are interpreted as unsigned integers, except that if Rc = 1 (the mulhw. instruction) the first three bits of the condition register 0 field are set by signed comparison of the result to zero.

The 64-bit operands are the contents of RA and RB. The low-order 64 bits of the 128-bit product of the operands are placed into RT.

Other registers altered:

Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)

Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 64-bit result.

This instruction may execute faster on some implementations if RB contains the operand having the smaller absolute value.

Parameters

RT	Specifies target general-purpose register for the result of the computation.
RA	Specifies source general-purpose register for the multiplicand.
RB	Specifies source general-purpose register for the multiplier.

Implementation

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.