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Assembler Language Reference

mtfsb1 (Move to FPSCR Bit 1) Instruction

Purpose

Sets a specified Floating-Point Status and Control Register bit to 1.

Syntax

Bits Value
0-5 63
6-10 BT
11-15 ///
16-20 ///
21-30 38
31 Rc
mtfsb1 BT
mtfsb1. BT

Description

The mtfsb1 instruction sets the Floating-Point Status and Control Register (FPSCR) bit specified by BT to 1.

The mtfsb1 instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form FPSCR Bits Record Bit (Rc) Condition Register Field 1
mtfsb1 None 0 None
mtfsb1. None 1 FX, FEX, VX, OX

The two syntax forms of the mtfsb1 instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Note: Bits 1-2 cannot be explicitly set or reset.

Parameters

BT Specifies that the FPSCR bit is set to 1 by instruction.

Examples

  1. The following code sets the Floating-Point Status and Control Register bit 4 to 1:

    mtfsb1 4
    # Now bit 4 of the Floating-Point Status and Control
    # Register is set to 1.
  2. The following code sets the Floating-Point Status and Control Register Overflow Exception Bit (bit 3) to 1 and sets Condition Register Field 1 to reflect the result of the operation:

    mtfsb1. 3
    # Now bit 3 of the Floating-Point Status and Control
    # Register is set to 1.

Related Information

Floating-Point Processor .

Interpreting the Contents of a Floating-Point Register .

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