Loads the contents of the Floating-Point Status and Control Register into a floating-point register and fills the upper 32 bits with ones.
| Bits | Value |
|---|---|
| 0-5 | 63 |
| 6-10 | FRT |
| 11-15 | /// |
| 16-20 | /// |
| 21-30 | 583 |
| 31 | Rc |
| mffs | FRT |
| mffs. | FRT |
The mffs instruction places the contents of the Floating-Point Status and Control Register into bits 32-63 of floating-point register (FPR) FRT. The bits 0-31 of floating-point register FRT are undefined.
The mffs instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
| Syntax Form | FPSCR bits | Record Bit (Rc) | Condition Register Field 1 |
| mffs | None | 0 | None |
| mffs. | None | 1 | FX, FEX, VX, OX |
The two syntax forms of the mffs instruction never affect the Floating-Point Status and Control Register fields. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.
| FRT | Specifies target floating-point register where result of operation is stored. |
The following code loads the contents of the Floating-Point Status and Control Register into FPR 14, and fills the upper 32 bits of that register with ones:
# Assume FPSCR contains 0x0000 0000. mffs 14 # FPR 14 now contains 0xFFFF FFFF 0000 0000.
Interpreting the Contents of a Floating-Point Register .
Functional Differences for POWER family and PowerPC Instructions .