Loads a halfword of data from a specified location in memory into a general-purpose register, sets the remaining 16 bits of the general-purpose register to 0, and possibly places the address in another general-purpose register.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | RT |
| 11-15 | RA |
| 16-20 | RB |
| 21-30 | 331 |
| 31 | / |
| lhzux | RT, RA, RB |
The lhzux instruction loads a halfword of data from a specified location in memory, addressed by the effective address (EA), into bits 16-31 of the target general-purpose register (GPR) RT and sets bits 0-15 of GPR RT to 0.
If GPR RA is not 0, the EA is the sum of the contents of GPR RA and GPR RB. If GPR RA is 0, then the EA is the contents of GPR RB.
If RA does not equal RT and RA does not equal 0, and the storage access does not cause an Alignment interrupt or a Data Storage interrupt, then the EA is placed into GPR RA.
The lhzux instruction has one syntax form and does not affect the Fixed-Point Exception Register.
The following code loads a halfword of data into bits 16-31 of GPR 6, sets bits 0-15 of GPR 6 to 0, and stores the effective address in GPR 5:
.csect data[rw] storage: .short 0xffff # Assume GPR 5 contains the address of csect data[rw]. # Assume GPR 4 contains the displacement of storage # relative to data[rw]. .csect text[pr] lhzux 6,5,4 # GPR 6 now contains 0x0000 ffff. # GPR 5 now contains the storage address.
Fixed-Point Load and Store with Update Instructions .