Assembler Language Reference

lfqx (Load Floating-Point Quad Indexed) Instruction

Purpose

Loads two double-precision values into floating-point registers.

Note: The lfqx instruction is supported only in the POWER2 implementation of the POWER family architecture.

Syntax

Bits	Value
0-5	31
6-10	FRT
11-15	RA
16-20	RB
21-30	791
31	Rc

POWER2
lfqx	FRT, RA, RB

Description

The lfqx instruction loads the two doublewords from the location in memory specified by the effective address (EA) into two floating-point registers (FPR).

If general-purpose register (GPR) RA is not 0, the EA is the sum of the contents of GPR RA and GPR RB. If GPR RA is 0, the EA is the contents of GPR RB. The doubleword at the EA is loaded into FPR FRT. If FRT is 31, the doubleword at EA+8 is loaded into FPR 0; otherwise, it is loaded into FRT+1.

The lfqx instruction has one syntax form and does not affect the Floating-Point Status and Control Register or Condition Register Field 0.

Parameters

FRT	Specifies the first of two target floating-point registers.
RA	Specifies one source general-purpose register for the EA calculation.
RB	Specifies the second source general-purpose register for the EA calculation.

Examples

The following code calculates the sum of two double-precision, floating-point values that are located in consecutive doublewords in memory:

# Assume GPR 3 contains the address of the first floating-point
# value.
# Assume GPR 4 contains the address of the target location.
lfqx    7,0,3            # Load values into FPRs 7 and 8.
fadd    7,7,8            # Add the two values.
stfdx   7,0,4            # Store the doubleword result.

Related Information

Floating-Point Processor .

Floating-Point Load and Store Instructions .