Assembler Language Reference

lfq (Load Floating-Point Quad) Instruction

Purpose

Loads two double-precision values into floating-point registers.

Note: The lfq instruction is supported only in the POWER2 implementation of the POWER family architecture.

Syntax

Bits	Value
0-5	56
6-10	FRT
11-15	RA
16-29	DS
30-31	00

POWER2
lfq	FRT, DS( RA)

Description

The lfq instruction loads the two doublewords from the location in memory specified by the effective address (EA) into two floating-point registers (FPR).

DS is sign-extended to 30 bits and concatenated on the right with b'00' to form the offset value. If general-purpose register (GPR) RA is 0, the offset value is the EA. If GPR RA is not 0, the offset value is added to GPR RA to generate the EA. The doubleword at the EA is loaded into FPR FRT. If FRT is 31, the doubleword at EA+8 is loaded into FPR 0; otherwise, it is loaded into FRT+1.

The lfq instruction has one syntax form and does not affect the Floating-Point Status and Control Register or Condition Register Field 0.

Parameters

FRT	Specifies the first of two target floating-point registers.
DS	Specifies a 14-bit field used as an immediate value for the EA calculation.
RA	Specifies one source general-purpose register for the EA calculation.

Examples

The following code copies two double-precision floating-point values from one place in memory to a second place in memory:

# Assume GPR 3 contains the address of the first source
# floating-point value.
# Assume GPR 4 contains the address of the target location.
lfq     7,0(3)          # Load first two values into FPRs 7 and
                        # 8.
stfq    7,0(4)          # Store the two doublewords at the new
                        # location.

Related Information

Floating-Point Processor .

Floating-Point Load and Store Instructions .