[ Bottom of Page | Previous Page | Next Page | Contents | Index | Library Home | Legal | Search ]

Assembler Language Reference

fnmadd or fnma (Floating Negative Multiply-Add) Instruction

Purpose

Multiplies two floating-point operands, adds the result to one floating-point operand, and places the negative of the result in a floating-point register.

Syntax

Bits Value
0-5 63
6-10 FRT
11-15 FRA
16-20 FRB
21-25 FRC
26-30 31
31 Rc
PowerPC 
fnmadd FRT, FRA, FRC, FRB
fnmadd. FRT, FRA, FRC, FRB
POWER family 
fnma FRT, FRA, FRC, FRB
fnma. FRT, FRA, FRC, FRB
Bits Value
0-5 59
6-10 FRT
11-15 FRA
16-20 FRB
21-25 FRC
26-30 31
31 Rc
PowerPC 
fnmadds FRT, FRA, FRC, FRB
fnmadds. FRT, FRA, FRC, FRB

Description

The fnmadd and fnma instructions multiply the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRA by the 64,bit, double-precision floating-point operand in FPR FRC, and add the 64-bit, double-precision floating-point operand in FPR FRB to the result of the multiplication.

The fnmadds instruction multiplies the 32-bit, single-precision floating-point operand in FPR FRA by the 32-bit, single-precision floating-point operand in FPR FRC, and adds the 32-bit, single-precision floating-point operand in FPR FRB to the result of the multiplication.

The result of the addition is rounded under control of the Floating-Point Rounding Control Field RN of the Floating-Point Status and Control Register.

Note: If an operand is a denormalized number, then it is prenormalized before the operation is begun.

The fnmadd and fnma instructions are identical to the fmadd and fma (Floating Multiply- Add Single) instructions with the final result negated, but with the following exceptions:

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation Exceptions, when the Floating-Point Invalid Operation Exception Enable bit is 1.

The fnmadd, fnmadds, and fnma instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

Syntax Form Floating-Point Status and Control Register Record Bit (Rc) Condition Register Field 1
fnmadd C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None
fnmadd. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX
fnmadds C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None
fnmadds. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX
fnma C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None
fnma. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX

All syntax forms of the fnmadd, fnmadds, and fnma instructions always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Note: Rounding occurs before the result of the addition is negated. Depending on RN, an inexact value may result.

Parameters

FRT Specifies target floating-point register for operation.
FRA Specifies source floating-point register for operation.
FRB Specifies source floating-point register for operation.
FRC Specifies source floating-point register for operation.

Examples

  1. The following code multiplies the contents of FPR 4 and FPR 5, adds the result to the contents of FPR 7, stores the negated result in FPR 6, and sets the Floating-Point Status and Control Register to reflect the result of the operation:

    # Assume FPR 4 contains 0xC053 4000 0000 0000.
    # Assume FPR 5 contains 0x400C 0000 0000 0000.
    # Assume FPR 7 contains 0x3DE2 6AB4 B33c 110A.
    # Assume FPSCR = 0.
    fnmadd 6,4,5,7
    # FPR 6 now contains 0x4070 D7FF FFFF F6CB.
    # FPSCR now contains 0x8206 4000.
  2. The following code multiplies the contents of FPR 4 and FPR 5, adds the result to the contents of FPR 7, stores the negated result in FPR 6, and sets the Floating-Point Status and Control Register and Condition Register Field 1 to reflect the result of the operation:

    # Assume FPR 4 contains 0xC053 4000 0000 0000.
    # Assume FPR 5 contains 0x400C 0000 0000 0000.
    # Assume FPR 7 contains 0x3DE2 6AB4 B33c 110A.
    # Assume FPSCR = 0 and CR = 0.
    fnmadd. 6,4,5,7
    # FPR 6 now contains 0x4070 D7FF FFFF F6CB.
    # FPSCR now contains 0x8206 4000.
    # CR now contains 0x0800 0000.

Related Information

Floating-Point Processor .

Interpreting the Contents of a Floating-Point Register .

[ Top of Page | Previous Page | Next Page | Contents | Index | Library Home | Legal | Search ]