Assembler Language Reference

fmul or fm (Floating Multiply) Instruction

Purpose

Multiplies two floating-point operands.

Syntax

Bits	Value
0-5	63
6-10	FRT
11-15	FRA
16-20	///
21-25	FRC
26-30	25
31	Rc

PowerPC
fmul	FRT, FRA, FRC
fmul.	FRT, FRA, FRC

POWER family
fm	FRT, FRA, FRC
fm.	FRT, FRA, FRC

Bits	Value
0-5	59
6-10	FRT
11-15	FRA
16-20	///
21-25	FRC
26-30	25
31	Rc

PowerPC
fmuls	FRT, FRA, FRC
fmuls.	FRT, FRA, FRC

Description

The fmul and fm instructions multiply the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRA by the 64-bit, double-precision floating-point operand in FPR FRC.

The fmuls instruction multiplies the 32-bit, single-precision floating-point operand in FPR FRA by the 32-bit, single-precision floating-point operand in FPR FRC.

The result is rounded under control of the Floating-Point Rounding Control Field RN of the Floating-Point Status and Control Register and is placed in the target FPR FRT.

Multiplication of two floating-point numbers is based on exponent addition and multiplication of the two significands.

Note: If an operand is a denormalized number, then it is prenormalized before the operation is begun.

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation Exceptions, when the Floating-Point Invalid Operation Exception Enable bit is 1.

The fmul, fmuls, and fm instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

Syntax Form	Floating-Point Status and Control Register	Record Bit (Rc)	Condition Register Field 1
fmul	C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXIMZ	0	None
fmul.	C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXIMZ	1	FX,FEX,VX,OX
fmuls	C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXIMZ	0	None
fmuls.	C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXIMZ	1	FX,FEX,VX,OX
fm	C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXIMZ	0	None
fm.	C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXIMZ	1	FX,FEX,VX,OX

All syntax forms of the fmul, fmuls, and fm instructions always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Parameters

FRT	Specifies target floating-point register for operation.
FRA	Specifies source floating-point register for operation.
FRC	Specifies source floating-point register for operation.

Examples

The following code multiplies the contents of FPR 4 and FPR 5, places the result in FPR 6, and sets the Floating-Point Status and Control Register to reflect the result of the operation:

# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPSCR = 0.
fmul 6,4,5
# FPR 6 now contains 0xC070 D800 0000 0000.
# FPSCR now contains 0x0000 8000.

The following code multiplies the contents of FPR 4 and FPR 25, places the result in FPR 6, and sets Condition Register Field 1 and the Floating-Point Status and Control Register to reflect the result of the operation:

# Assume FPR  4 contains 0xC053 4000 0000 0000.
# Assume FPR 25 contains 0xFFFF FFFF FFFF FFFF.
# Assume FPSCR = 0 and CR = 0.
fmul. 6,4,25
# FPR 6 now contains 0xFFFF FFFF FFFF FFFF.
# FPSCR now contains 0x0001 1000.
# CR now contains 0x0000 0000.

Related Information

Floating-Point Processor .

Floating-Point Arithmetic Instructions .

Interpreting the Contents of a Floating-Point Register .