Assembler Language Reference

fdiv or fd (Floating Divide) Instruction

Purpose

Divides one floating-point operand by another.

Syntax

Bits	Value
0-5	63
6-10	FRT
11-15	FRA
16-20	FRB
21-25	///
26-30	18
31	Rc

PowerPC
fdiv	FRT, FRA, FRB
fdiv.	FRT, FRA, FRB

POWER family
fd	FRT, FRA, FRB
fd.	FRT, FRA, FRB

Bits	Value
0-5	59
6-10	FRT
11-15	FRA
16-20	FRB
21-25	///
26-30	18
31	Rc

PowerPC
fdivs	FRT, FRA, FRB
fdivs.	FRT, FRA, FRB

Description

The fdiv and fd instructions divide the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRA by the 64-bit, double-precision floating-point operand in FPR FRB. No remainder is preserved.

The fdivs instruction divides the 32-bit single-precision floating-point operand in FPR FRA by the 32-bit single-precision floating-point operand in FPR FRB. No remainder is preserved.

The result is rounded under control of the Floating-Point Rounding Control Field RN of the Floating-Point Status and Control Register (FPSCR), and is placed in the target FPR FRT.

The floating-point division operation is based on exponent subtraction and division of the two significands.

Note: If an operand is a denormalized number, then it is prenormalized before the operation is begun.

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation Exceptions, when the Floating-Point Invalid Operation Exception Enable bit is 1.

The fdiv, fdivs, and fd instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

Syntax Form	Floating-Point Status and Control Register	Record Bit (Rc)	Condition Register Field 1
fdiv	C,FL,FG,FE,FU,FR,FI,OX,UX, ZX,XX,VXSNAN,VXIDI,VXZDZ	0	None
fdiv.	C,FL,FG,FE,FU,FR,FI,OX,UX, ZX,XX,VXSNAN,VXIDI,VXZDZ	1	FX,FEX,VX,OX
fdivs	C,FL,FG,FE,FU,FR,FI,OX,UX, ZX,XX,VXSNAN,VXIDI,VXZDZ	0	None
fdivs.	C,FL,FG,FE,FU,FR,FI,OX,UX, ZX,XX,VXSNAN,VXIDI,VXZDZ	1	FX,FEX,VX,OX
fd	C,FL,FG,FE,FU,FR,FI,OX,UX, ZX,XX,VXSNAN,VXIDI,VXZDZ	0	None
fd.	C,FL,FG,FE,FU,FR,FI,OX,UX, ZX,XX,VXSNAN,VXIDI,VXZDZ	1	FX,FEX,VX,OX

All syntax forms of the fdiv, fdivs, and fd instructions always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Parameters

FRT	Specifies target floating-point register for operation.
FRA	Specifies source floating-point register containing the dividend.
FRB	Specifies source floating-point register containing the divisor.

Examples

The following code divides the contents of FPR 4 by the contents of FPR 5, places the result in FPR 6, and sets the Floating-Point Status and Control Register to reflect the result of the operation:

# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPSCR = 0.
fdiv 6,4,5
# FPR 6 now contains 0xC036 0000 0000 0000.
# FPSCR now contains 0x0000 8000.

The following code divides the contents of FPR 4 by the contents of FPR 5, places the result in FPR 6, and sets Condition Register Field 1 and the Floating-Point Status and Control Register to reflect the result of the operation:

# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPSCR = 0.
fdiv. 6,4,5
# FPR 6 now contains 0xC036 0000 0000 0000.
# FPSCR now contains 0x0000 8000.
# CR contains 0x0000 0000.

Related Information

Floating-Point Processor .

Floating-Point Arithmetic Instructions .

Interpreting the Contents of a Floating-Point Register .