Convert the fixed-point contents of a floating-point register to a double-precision floating-point number.
| Bits | Value |
|---|---|
| 0-5 | 63 |
| 6-10 | D |
| 11-15 | 00000 |
| 16-20 | B |
| 21-30 | 846 |
| 31 | Rc |
| PowerPC | |
|---|---|
| fcfid | FRT, FRB (Rc=0) |
| fcfid. | FRT, FRB (Rc=1) |
The 64-bit signed fixed-point operand in floating-point register (FPR) FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision using the rounding mode specified by FPSCR[RN] and placed into FPR FRT.
FPSCR[FPRF] is set to the class and sign of the result. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact.
The fcfid instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
| Syntax Form | Floating-Point Status and Control Register | Record Bit (Rc) | Condition Register Field 1 |
| fcfid | FPRF,FR,FI,FX,XX | 0 | None |
| fcfid. | FPRF,FR,FI,FX,XX | 1 | FX,FEX,VX,OX |
| FRT | Specifies the target floating-point register for the operation. |
| FRB | Specifies the source floating-point register for the operation. |
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.