Count the number of consecutive zero bits in the contents of a general purpose register, beginning with the high-order bit.
This instruction should only be used on 64-bit PowerPC processors running a 64-bit application.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | S |
| 11-15 | A |
| 16-20 | 00000 |
| 21-30 | 58 |
| 31 | Rc |
| PowerPC64 | |
|---|---|
| cntlzd | rA, rS (Rc=0) |
| cntlzd. | rA, rS(Rc=1) |
A count of the number of consecutive zero bits, starting at bit 0 (the high-order bit) of register GPR RS is placed into GPR RA. This number ranges from 0 to 64, inclusive.
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
Note: If Rc = 1, then LT is cleard in the CR0 field.
| RA | Specifies the target general purpose register for the results of the instruction. |
| RS | Specifies the source general purpose register containing the double-word to examine. |
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.