Rotates the contents of a general-purpose register to the left by a specified number of bits, merges the result with the contents of the MQ Register under control of a generated mask, and places the result in another general-purpose register.
Note: The srliq instruction is supported only in the POWER architecture.
The srliq instruction rotates the contents of the source general-purpose register (GPR) RS to the left by 32 minus N bits, where N is the shift amount specified by SH, merges the result with the contents of the MQ Register under control of a generated mask, and stores the rotated word in the MQ Register and the merged result in GPR RA. The mask consists of N zeros followed by 32 minus N ones.
The srliq instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.
|Syntax Form||Overflow Exception (OE)||Fixed-Point Exception Register||Record Bit (Rc)||Condition Register Field 0|
The two syntax forms of the srliq instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.
|RA||Specifies target general-purpose register where result of operation is stored.|
|RS||Specifies source general-purpose register for operation.|
|SH||Specifies value for shift amount.|
# Assume GPR 4 contains 0x9000 300F. # Assume the MQ Register contains 0x1111 1111. srliq 6,4,0x4 # GPR 6 now contains 0x1900 0300. # The MQ Register now contains 0xF900 0300.
# Assume GPR 4 contains 0xB004 3000 # Assume the MQ Register contains 0xFFFF FFFF. srliq. 6,4,0x4 # GPR 6 now contains 0xFB00 4300. # The MQ Register contains 0x0B00 4300. # Condition Register Field 0 now contains 0x8.
Fixed-Point Rotate and Shift Instructions.