Shifts the contents of a general-purpose register to the right by a specified number of bits and places a copy of the rotated data in the MQ Register and the result in a general-purpose register.
Note: The sre instruction is supported only in the POWER architecture.
The sre instruction rotates the contents of the source general-purpose register (GPR) RS to the left by 32 minus N bits, where N is the shift amount specified in bits 27-31 of GPR RB, and stores the rotated word in the MQ Register and the logical AND of the rotated word and a generated mask in GPR RA. The mask consists of N zeros followed by 32 minus N ones.
The sre instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.
|Syntax Form||Overflow Exception (OE)||Fixed-Point Exception Register||Record Bit (Rc)||Condition Register Field 0|
The two syntax forms of the sre instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.
|RA||Specifies target general-purpose register where result of operation is stored.|
|RS||Specifies source general-purpose register for operation.|
|RB||Specifies source general-purpose register for operation.|
# Assume GPR 4 contains 0x9000 3000. # Assume GPR 5 contains 0x0000 000C. sre 6,4,5 # GPR 6 now contains 0x0009 0003. # The MQ Register now contains 0x0009 0003.
# Assume GPR 4 contains 0xB004 3000. # Assume GPR 5 contains 0x0000 000F. sre. 6,4,5 # GPR 6 now contains 0x0001 6008. # The MQ Register now contains 0x6001 6008. # Condition Register Field 0 now contains 0x4.
Fixed-Point Rotate and Shift Instructions.