This section discusses the following:
The following instructions are available in POWER and PowerPC. These instructions share the same op code and mnemonic, and have the same function in POWER and PowerPC, but use different input operand formats.
The input operand format for POWER is:
BF, RA, SI | RB | UI
The input operand format for PowerPC is:
BF, L, RA, SI | RB | UI
The assembler handles these as the same instructions in POWER and PowerPC, but with different input operand formats. The L operand is one bit. For POWER, the assembler presets this bit to 0. For 32-bit PowerPC platforms, this bit must be set to 0, or an invalid instruction form results.
The instructions listed in the following table are available in POWER and PowerPC. These instructions share the same op code and function, but have different mnemonics and input operand formats. The assembler still places them in the POWER/PowerPC intersection area, because the same binary code is generated. If the -s option is used, no cross-reference is given, because it is necessary to change the source code when migrating from POWER to PowerPC, or vice versa.
|Instructions with Same Op Code and Function|
- lil is an extended mnemonic of cal, and li is an extended mnemonic of addi. Since the op code, function, and input operand format are the same, the assembler provides a cross-reference for lil and li.
- liu is an extended mnemonic of cau, and lis is an extended mnemonic of addis. Since the input operand format is different, the assembler does not provide a cross-reference for liu and lis.
- The immediate value for the cau instruction is a 16-bit unsigned integer, while the immediate value for the addis instruction is a 16-bit signed integer. The assembler performs a (0, 65535) value range check for the UI field and a (-32768, 32767) value range check for the SI field.
To maintain source compatibility of the cau and addis instructions, the assembler expands the value range check to (-65536, 65535) for the addis instruction. The sign bit is ignored and the assembler ensures only that the immediate value fits in 16 bits. This expansion does not affect the behavior of a 32-bit implementation.
For a 64-bit implementation, if bit 32 is set, it is propagated through the upper 32 bits of the 64-bit general-purpose register (GPR). Therefore, if an immediate value within the range (32768, 65535) or (-65536, -32767) is used for the addis instruction in a 32-bit mode, this immediate value may not be directly ported to a 64-bit mode.
Moving from the DEC (decrement) special purpose register is privileged in PowerPC, but nonprivileged in POWER. One bit in the instruction field that specifies the register is 1 for privileged operations, but 0 for nonprivileged operations. As a result, the encoding number for the DEC SPR for the mfdec instruction has different values in PowerPC and POWER. The DEC encoding number is 22 for PowerPC and 6 for POWER. If the mfdec instruction is used, the assembler determines the DEC encoding based on the current assembly mode. The following list shows the assembler processing of the mfdec instruction for each assembly mode value:
Migrating POWER and PowerPC Source Programs.
Functional Differences for POWER and PowerPC Instructions.
Extended Mnemonics Changes.
POWER Instructions Deleted from PowerPC.
New PowerPC Instructions.
Instructions Available Only for the PowerPC 601 RISC Microprocessor.