Sets a specified Floating-Point Status and Control Register bit to 1.
The mtfsb1 instruction sets the Floating-Point Status and Control Register (FPSCR) bit specified by BT to 1.
The mtfsb1 instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.
|Syntax Form||FPSCR Bits||Record Bit (Rc)||Condition Register Field 1|
|mtfsb1.||None||1||FX, FEX, VX, OX|
The two syntax forms of the mtfsb1 instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.
Note: Bits 1-2 cannot be explicitly set or reset.
|BT||Specifies that the FPSCR bit is set to 1 by instruction.|
mtfsb1 4 # Now bit 4 of the Floating-Point Status and Control # Register is set to 1.
mtfsb1. 3 # Now bit 3 of the Floating-Point Status and Control # Register is set to 1.
Interpreting the Contents of a Floating-Point Register.