mtfsb1 (Move to FPSCR Bit 1) Instruction

Purpose

Sets a specified Floating-Point Status and Control Register bit to 1.

Syntax

Description

The mtfsb1 instruction sets the Floating-Point Status and Control Register (FPSCR) bit specified by BT to 1.

The mtfsb1 instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

The two syntax forms of the mtfsb1 instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Note: Bits 1-2 cannot be explicitly set or reset.

Parameters

Examples

1. The following code sets the Floating-Point Status and Control Register bit 4 to 1:

   mtfsb1 4
   # Now bit 4 of the Floating-Point Status and Control
   # Register is set to 1.

2. The following code sets the Floating-Point Status and Control Register Overflow Exception Bit (bit 3) to 1 and sets Condition Register Field 1 to reflect the result of the operation:

   mtfsb1. 3
   # Now bit 3 of the Floating-Point Status and Control
   # Register is set to 1.

Related Information

Floating-Point Processor.

Interpreting the Contents of a Floating-Point Register.