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AIX Version 4.3 Assembler Language Reference

## lhaux (Load Half Algebraic with Update Indexed) Instruction

### Purpose

Loads a halfword of data from a specified location in memory into a general-purpose register, copies bit 0 of the halfword into the remaining 16 bits of the general-purpose register, and possibly places the address in another general-purpose register.

### Syntax

 lhaux RT,RA,RB

### Description

The lhaux instruction loads a halfword of data from a specified location in memory addressed by the effective address (EA) into bits 16-31 of the target general-purpose register (GPR) RT and copies bit 0 of the halfword into bits 0-15 of GPR RT.

If GPR RA is not 0, the EA is the sum of the contents of GPR RA and GPR RB. If GPR RA is 0, then the EA is the contents of GPR RB.

If RA does not equal RT and RA does not equal 0, and the storage access does not cause an Alignment interrupt or a Data Storage interrupt, then the EA is placed into GPR RA.

The lhaux instruction has one syntax form and does not affect the Fixed-Point Exception Register.

### Parameters

 RT Specifies target general-purpose register where result of operation is stored. RA Specifies first source general-purpose register for EA calculation and possible address update. RB Specifies second source general-purpose register for EA calculation.

### Examples

The following code loads a halfword of data into bits 16-31 of GPR 6, copies bit 0 of the halfword into bits 0-15 of GPR 6, and stores the effective address in GPR 5:

```.csect data[rw]
storage: .short 0xffff
# Assume GPR 5 contains the address of csect data[rw].
# Assume GPR 4 contains the displacement of storage relative
# to data[rw].
.csect text[pr]
lhaux 6,5,4
# GPR 6 now contains 0xffff ffff.
# GPR 5 now contains the storage address.```

### Related Information

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