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AIX Version 4.3 Assembler Language Reference

lbzu (Load Byte and Zero with Update) Instruction


Loads a byte of data from a specified location in memory into a general-purpose register, sets the remaining 24 bits to 0, and possibly places the address in a second general-purpose register.


lbzu RT,D(RA)


The lbzu instruction loads a byte in storage addressed by the effective address (EA) into bits 24-31 of the target general-purpose register (GPR) RT and sets bits 0-23 of GPR RT to 0.

If RA is not 0, the EA is the sum of the contents of GPR RA and D, a 16-bit signed two's complement integer sign extended to 32 bits. If RA is 0, then the EA is D.

If RA does not equal RT and RA does not equal 0, and the storage access does not cause an Alignment interrupt or a Data Storage interrupt, then the EA is stored in GPR RA.

The lbzu instruction has one syntax form and does not affect the Fixed-Point Exception Register or Condition Register Field 0.


RT Specifies target general-purpose register where result of operation is stored.
D 16-bit, signed two's complement integer sign-extended to 32 bits for EA calculation.
RA Specifies source general-purpose register for EA calculation and possible address update.


The following code loads a byte of data from a specified location in memory into GPR 6, sets the remaining 24 bits to 0, and places the address in GPR 5:

.csect data[rw]
storage:  .byte 0x61
# Assume GPR 5 contains the address of csect data[rw].
.csect text[pr]
lbzu 6,storage(5)
# GPR 6 now contains 0x0000 0061.
# GPR 5 now contains the storage address.

Related Information

Fixed-Point Processor.

Fixed-Point Load and Store with Update Instructions.

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