Calculates a single-precision estimate of the reciprocal of a floating-point operand.
Note: The fres instruction is defined only in the PowerPC architecture and is an optional instruction. It is supported on the PowerPC 603 RISC Microprocessor, and PowerPC 604 RISC Microprocessor, but not supported on the PowerPC 601 RISC Microprocessor.
| PowerPC | |
|---|---|
| fres | FRT,FRB |
| fres. | FRT,FRB |
The fres instruction calculates a single-precision estimate of the reciprocal of the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRB and places the result in FPR FRT.
The estimate placed into register FRT is correct to a precision of one part in 256 of the reciprocal of FRB. The value placed into FRT may vary between implementations, and between different executions on the same implementation.
The following table summarizes special conditions:
| Special Conditions | ||
| Operand | Result | Exception |
| Negative Infinity | Negative 0 | None |
| Negative 0 | Negative Infinity1 | ZX |
| Positive 0 | Positive Infinity1 | ZX |
| Positive Infinity | Positive 0 | None |
| SNaN | QNaN2 | VXSNAN |
| QNaN | QNaN | None |
FPSCRFPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when FPSCRVE = 1 and Zero Divide Exceptions when FPSCRZE = 1.
The fres instruction has two syntax forms. Both syntax forms always affect the FPSCR register. Each syntax form has a different effect on Condition Register Field 1.
| Syntax Form | Floating-Point Status and Control Register | Record Bit (Rc) | Condition Register Field 1 |
| fres | C,FL,FG,FE,FU,FR,FI,FX,OX, UX,ZX,VXSNAN | 0 | None |
| fres. | C,FL,FG,FE,FU,FR,FI,FX,OX, UX,ZX,VXSNAN | 1 | FX,FEX,VX,OX |
The fres. syntax form sets the Record (Rc) bit to 1; and the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1 (CR1). The fres syntax form sets the Record (Rc) bit to 0 and does not affect Condition Register Field 1 (CR1).
| FRT | Specifies target floating-point register for operation. |
| FRB | Specifies source floating-point register for operation. |
Floating-Point Arithmetic Instructions.
Interpreting the Contents of a Floating-Point Register.