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AIX Version 4.3 Assembler Language Reference

## fnmsub or fnms (Floating Negative Multiply-Subtract) Instruction

### Purpose

Multiplies two floating-point operands, subtracts one floating-point operand from the result, and places the negative of the result in a floating-point register.

### Syntax

PowerPC
fnmsub FRT,FRA,FRC,FRB
fnmsub. FRT,FRA,FRC,FRB
POWER
fnms FRT,FRA,FRC,FRB
fnms. FRT,FRA,FRC,FRB

PowerPC
fnmsubs FRT,FRA,FRC,FRB
fnmsubs. FRT,FRA,FRC,FRB

### Description

The fnms and fnmsub instructions multiply the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRA by the 64,-bit double-precision floating-point operand in FPR FRC, subtract the 64-bit, double-precision floating-point operand in FPR FRB from the result of the multiplication, and place the negated result in the target FPR FRT.

The fnmsubs instruction multiplies the 32-bit, single-precision floating-point operand in FPR FRA by the 32-bit, single-precision floating-point operand in FPR FRC, subtracts the 32-bit, single-precision floating-point operand in FPR FRB from the result of the multiplication, and places the negated result in the target FPR FRT.

The subtraction result is rounded under control of the Floating-Point Rounding Control Field RN of the Floating-Point Status and Control Register.

Note: If an operand is a denormalized number, then it is prenormalized before the operation is begun.

The fnms and fnmsub instructions are identical to the fmsub and fms (Floating Multiply-Subtract Single) instructions with the final result negated, but with the following exceptions:

• Quiet NaNs (QNaNs) propagate with no effect on their "sign" bit.
• QNaNs that are generated as the result of a disabled Invalid Operation Exception have a "sign" bit of zero.
• Signaling NaNs (SNaNs) that are converted to QNaNs as the result of a disabled Invalid Operation Exception have no effect on their "sign" bit.

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation Exceptions, when the Floating-Point Invalid Operation Exception Enable bit is 1.

The fnmsub, fnmsubs, and fnms instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

 Syntax Form Floating-Point Status and Control Register Record Bit (Rc) Condition Register Field 1 fnmsub C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None fnmsub. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX fnmsubs C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None fnmsubs. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX fnms C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None fnms. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX

All syntax forms of the fnmsub, fnmsubs, and fnms instructions always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Note: Rounding occurs before the result of the addition is negated. Depending on RN, an inexact value may result.

### Parameters

 FRT Specifies target floating-point register for operation. FRA Specifies first source floating-point register for operation. FRB Specifies second source floating-point register for operation. FRC Specifies third source floating-point register for operation.

### Examples

1. The following code multiplies the contents of FPR 4 and FPR 5, subtracts the contents of FPR 7 from the result, stores the negated result in FPR 6, and sets the Floating-Point Status and Control Register and Condition Register Field 1 to reflect the result of the operation:
```# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPR 7 contains 0x3DE2 6AB4 B33c 110A.
# Assume FPSCR = 0.
fnmsub 6,4,5,7
# FPR 6 now contains 0x4070 D800 0000 0935.
# FPSCR now contains 0x8202 4000.```
2. The following code multiplies the contents of FPR 4 and FPR 5, subtracts the contents of FPR 7 from the result, stores the negated result in FPR 6, and sets the Floating-Point Status and Control Register and Condition Register Field 1 to reflect the result of the operation:
```# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPR 7 contains 0x3DE2 6AB4 B33c 110A.
# Assume FPSCR = 0 and CR = 0.
fnmsub. 6,4,5,7
# FPR 6 now contains 0x4070 D800 0000 0935.
# FPSCR now contains 0x8202 4000.
# CR now contains 0x0800 0000.```

### Related Information

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