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AIX Version 4.3 Assembler Language Reference

andis. or andiu. (AND Immediate Shifted) Instruction


Logically ANDs the most significant 16 bits of the contents of a general-purpose register with a 16-bit unsigned integer and stores the result in a general-purpose register.


andis. RA,RS,UI
andiu. RA,RS,UI


The andis. and andiu. instructions logically AND the contents of general-purpose register (GPR) RS with the concatenation of a 16-bit unsigned integer, UI, and x'0000' and then place the result into the target GPR RA.

The andis. and andiu. instructions have one syntax form and never affect the Fixed-Point Exception Register. The andis. and andiu. instructions set the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, or Summary Overflow (SO) bit in Condition Register Field 0.


RA Specifies target general-purpose register where result of operation is stored.
RS Specifies source general-purpose register for operation.
UI Specifies 16-bit unsigned integer for operation.


The following code logically ANDs the contents of GPR 4 with 0x5730 0000, stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:

# Assume GPR 4 contains 0x7B41 92C0.
andis. 6,4,0x5730
# GPR 6 now contains 0x5300 0000.

Related Information

Fixed-Point Processor.

Fixed-Point Logical Instructions.

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