|5FEC ::: QUATECH QS-2000 Quad Port Asynchronous RS-422|
5FEC ::: QUATECH QS-3000 Quad Port Asynchronous RS-485
Technical information contained in this page are edited excerpts from the QUATECH Reference Manual (qs-2000.pdf), Copyright © Quatech Inc.
|Bus interface||MicroChannel 16-bit|
|Interface||D-37 female connector *|
Quad 6-wire RJ-11 (optional) *
|I/O address range||0000H - FFFFH (block mode)|
Serial 1 - Serial 8 (discrete mode)
|Interrupt levels||IRQ 3, 4, 9|
|1425mA typical, 1618mA maximum at +5V|
|1372mA typical, 1566mA maximum at +5V|
* Connector pinouts are described in the QS-2000/QS-3000 Reference Manual.
The Quatech (Qua Tech) QS-2000 provides four independent asynchronous RS-422 serial communication channels for systems utilizing the MicroChannel architecture. The QS-3000 is an RS-485 version of the adapter. Each port may be accessed individually from the predefined addresses of Serial 1 through Serial 8 or the four channels may be grouped together and located anywhere within the available I/O address range of the system. Two output options increase flexibility by allowing connection to a 37-pin 'D' connector (D-37) or an abbreviated 6-wire RJ-11 modular phone jack style connector.
The QS-2000/QS-3000 serial interface is realized through four 16550 ACEs (Asynchronous Communication Elements). The 16550 is compatible with the 8250 and 16450 ACEs used in the PC/XT/AT models. In addition, the 16550 supports a FIFO mode to reduce CPU overhead at higher data rates.
The QS-2000/QS-3000 address and interrupt selections are accessed through the Programmable Option Select using the IBM installation utilities. In addition, jumpers are provided to select input clock frequency and control of the data exchanged on the auxiliary channel.
The 16550 is an upgrade of the standard 16450 Asynchronous Communications Element (ACE). Designed to be compatible with the 16450, the 16550 enters the character mode on reset and in this mode will appear as a 16450 to user software. An additional mode, FIFO mode, can be selected to reduce CPU overhead at high data rates. The FIFO mode increases performance by providing two internal 16-byte FIFOs (one transmit and one receive) to buffer data and reduce the number of interrupts issued to the CPU.
Baud Rate Selection
The 16550 ACE determines the baud rate of the serial output from a combination of the clock input frequency and the value written to the divisor latches. Standard PC, PC/XT, PC/AT, and PS/2 serial interfaces use an input clock of 1.8432 MHz. To increase versatility, the QS-2000/QS-3000 uses an 18.432 MHz clock and a frequency divider circuit to produce the standard clock frequency.
Jumper block J5 is used to set the input frequency to the 16550. It may be connected to divide the clock input by 1, 2, 5, or 10. To maintain compatibility with adapters using a 1.8432 MHz input, J1 should be configured to divide by 10. Consult the QS-2000/QS-3000 Reference Manual for the table of divisor latch values for various input frequencies.
Each channel of the QS-2000/QS-3000 uses eight consecutive I/O address locations beginning on an even 8 byte boundary (xxx0H - xxx7H) or (xxx8H - xxxFH). Two addressing modes are available on the QS-1000: discrete addressing and block addressing.
WARNING: In block mode, each channel may be individually disabled, but the I/O space assigned to that channel is still considered in use and may not be used by another device.
NOTE: To change the addressing mode, physically remove the QS-2000/QS-3000 from the system, configure the system with the reference diskette, physically reinsert the QS-2000/QS-3000 and configure again the system with the reference diskette (UZ).
Four sets of jumpers are implemented on the QS-2000/QS-3000 to control the auxiliary driver/receiver set. J1 through J4 perform the identical functions on channels 1 through 4 respectively.
Auxiliary Channel Configuration
The following discussion pertains to the control of the information exchanged on the auxiliary channel of the QS-2000/QS-3000. Since the auxiliary channel is not supported with the RJ-11 connector option, these users should set jumpers J1 - J4 to loopback all of the auxiliary channel signals and skip to "Half Duplex Operation".
The function of J1 through J4 is to control the source of the information exchanged on the auxiliary communication lines. The output sources are request to send (RTS), transmit clock (XCLK), and the auxiliary input (AUX IN). The inputs are clear to send (CTS) and receive clock (RCLK).
Transmission of RTS, when combined with reception of CTS, allows for handshaking between the 1650 and a peripheral device. RTS is transmitted by connecting pins 5 and 6 of the jumper block. CTS is received by connecting pins 1 and 2. The RTS/CTS handshake can be defeated by looping the RTS output back to the CTS input. This is accomplished by connecting pins 1 and 5.
RCLK is the input to the 16550 that controls the shift rate of the receiver portion of the chip. Generally, this input is provided by connecting it to the transmit clock, XCLK, output from the ACE. This is accomplished by connecting pins 3 and 7 of the jumper. RCLK may be received from an external source by connecting pins 2 and 3. Transmission of XCLK can be used to synchronize communications with a peripheral or to provide a shift clock to a receiver. XCLK is transmitted by connecting pins 6 and 7 of the jumper block.
AUX IN is the auxiliary input from a peripheral device. Connecting AUX IN to AUX OUT provides a loopback mode of operation. That is, whatever is transmitted by the peripheral will be fed back to the peripheral. This is implemented by connecting pins 2 and 6 of the jumper block.
Half Duplex Operation
The other function of J1 through J4 is to configure the communication channel in half or full duplex mode. Half duplex operation is achieved by connecting pins 4 and 8 of the jumper block. This allows the transmitter to be enabled and disabled using the data terminal ready (DTR) output controlled through the modem control register. When DTR is set (logic 1), the transmitter driver is enabled for both the data and auxiliary channel output. When cleared (logic 0), both outputs enter high impedance states. Full duplex communication is restored by removing the jumper on pins 4 and 8.
CAUTION: When operating in half duplex mode, the transmitter must be disabled before receiving any information. Failure to do so will result in two output drivers being connected together which may cause damage to the adapter, the computer, and/or the peripheral equipment.
The QS-2000/QS-3000 is available with two output configurations. The first option uses a female D-37 connector labeled CN1 on the circuit board. This configuration can provide all of the signals for each channel. The second option uses a quad 6-wire RJ-11 phone jack style connector labeled CN2 on the circuit board. This configuration provides only transmit and receive. Both output configurations have optional adapter cables to provide standard D-25 connectors for each channel. The various connectors and pinouts are described in detail in the QS-2000/QS-3000 Reference Manual.
ADF Adapter Description File
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