|5FE3 ::: QUATECH DS-2000 Dual Asynchronous RS-422|
5FE3 ::: QUATECH DS-3000 Dual Asynchronous RS-485
Technical information contained in this page are edited excerpts from the QUATECH Reference Manual (ds-2000.pdf), Copyright © Quatech Inc.
|Bus interface||MicroChannel 16-bit|
|RS-422 Interface||Two D-9 female connectors *|
|Transmit drivers||MC3486 or compatible|
|Receive buffers||MC3487 or compatible|
|I/O address range||16 base addresses selected through POS|
|Interrupt levels||IRQ 3, 4, 7, 9|
|Power requirements||630mA typical, 720mA maximum at +5V|
* Connector pinout is described in the DS-2000 Reference Manual.
The DS-2000 is a dual channel asynchronous serial communication adapter which utilizes balanced differential drivers and receivers to provide RS-422-A communications. It is capable of reliable communications over long distances (4000 feet) within noisy industrial environment. Data is communicated through two D-9 connectors which provide shielding from environmental noise. Optional high speed transient suppressers may also be installed on the DS-2000 to further reduce the effects of environmental signal transients and surges.
The serial interface is accomplished through a pair of 16550 Asynchronous Communication Elements (ACEs). The 16550 is compatible with the 8250 and 16450 ACEs used in the IBM PC/XT/AT models. The 16550 also has an additional FIFO mode that reduces CPU overhead at higher data rates.
The DS-2000 supports sixteen base addresses for each ACE through the Programmable Option Select (POS) including the eight addresses designated SERIAL 1 through SERIAL 8. The addresses are independent for each channel. CPU interrupt level selections are also handled through the POS. Each channel may select a separate interrupt or share an interrupt level with other devices.
The 16550 is an upgrade of the standard 16450 Asynchronous Communications Element (ACE). Designed to be compatible with the 16450, the 16550 enters the character mode on reset and in this mode will appear as a 16450 to user software. An additional mode, FIFO mode, can be selected to reduce CPU overhead at high data rates. The FIFO mode increases performance by providing two internal 16-byte FIFOs (one transmit and one receive) to buffer data and reduce the number of interrupts issued to the CPU.
Baud Rate Selection
The 16550 ACE determines the baud rate of the serial output from a combination of the clock input frequency and the value written to the divisor latches. Standard PC, PC/XT, PC/AT, and PS/2 serial interfaces use an input clock of 1.8432 MHz. To increase versatility, the DS-2000 uses an 18.432 MHz clock and a frequency divider circuit to produce the standard clock frequency. Jumper block J1 is used to set the input frequency to the 16550. It may be connected to divide the clock input by 1, 2, 5, or 10. To maintain compatibility with adapters using a 1.8432 MHz input, J1 should be configured to divide by 10. Consult the DS-2000 Reference Manual for the table of divisor latch values for various input frequencies.
Each channel of the DS-2000 uses 8 consecutive I/O address locations. The base addresses are independent but must begin on an even 8-byte boundary (xxx0H - xxx7H or xxx8H - xxxFH). The numbers xxx are controlled by the Programmable Option Select (POS) and address decoders to provide complete 16-bit addressing for each channel. Sixteen choices of base address are provided for each channel and include the eight addresses defined as SERIAL 1 through SERIAL 8. The remaining eight addresses are a constant 8000H offset from these values. A complete table of available addresses may be found in the DS-2000 Reference Manual.
Two sets of jumpers are implemented on the DS-2000 to control the auxiliary driver/receiver set. Jumpers J2 and J3 perform identical functions on channels 1 and 2 respectively.
The function of J2 and J3 is to control the source of the data exchanged on the auxiliary communication lines. The output sources are request to send (RTS), transmit clock (XCLK), and the auxiliary input (AUX IN). The inputs are clear to send (CTS) and receive clock (RCLK).
Transmission of RTS, when combined with reception of clear to send (CTS), allows for handshaking between the 16550 and a peripheral device. RTS is transmitted by connecting pins 5 and 6 of the jumper block. CTS is received by connecting pins 1 and 2. The RTS/CTS handshake can be defeated by looping the RTS output back to the CTS input. This is accomplished by connecting pins 1 and 5 of the jumper block.
RCLK is the input to the 16550 which controls the shift rate for the receiver portion of the chip. Generally this input is provided by connecting it to the XCLK output. This is performed by connecting pins 3 and 7 of the jumper block. RCLK may be received from an external source by connecting pins 2 and 3. Transmission of XCLK can be used to help synchronize communications with a peripheral or to provide a shift clock for a receiver. Transmission of XCLK is accomplished by connecting pins 6 and 7 of the jumper block.
AUX IN is the auxiliary input from a peripheral device. Connecting AUX IN to AUX OUT provides a loopback mode of operation. That is, whatever is transmitted by the peripheral will be fed back to the peripheral. AUX IN/ AUX OUT loopback is implemented by connecting pins 2 and 6 of the jumper.
Half Duplex Operation
The other function of J2 and J3 is to configure the communication channel in half or full duplex mode. Half duplex operation is achieved by connecting pins 4 and 8 of the jumper block. This allows the transmitter to be enabled and disabled using the data terminal ready (DTR) output in the modem control register. Full duplex operation is restored by removing the jumper on pins 4 and 8.
Jumper J4 selects the level of DTR that enables the transmitter outputs. When the enable control line is connected to +DTR (factory configuration), writing a logic 1 to the DTR bit location in the MODEM control register enabled transmission. Writing a logic 0 disables transmission. In this configuration, transmission is disabled on power-up.
To maintain compatibility with some other Quatech products, the enable control line can be connected to -DTR. In this configuration, writing a logic 0 to the DTR bit location in the MODEM control register enables transmission, logic 1 disables transmission. In this configuration, transmission is enabled on power-up.
CAUTION: When operating in half duplex mode, the transmitter must be disabled before receiving any information. Failure to do so will result in two output drivers being connected together which may cause damage to the adapter, the computer, and/or the peripheral equipment.
ADF Adapter Description File
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