tlbie or tlbi (Translation Look-Aside Buffer Invalidate Entry) Instruction

Purpose

Makes a translation look-aside buffer entry invalid for subsequent address translations.

Notes:

1. The tlbie instruction is optional for the PowerPC architecture. It is supported on PowerPC 601 RISC Microprocessor, PowerPC 603 RISC Microprocessor and PowerPC 604 RISC Microprocessor.
2. tlbi is a POWER instruction.

Syntax

Description

The PowerPC instruction tlbie searches the Translation Look-Aside Buffer (TLB) for an entry corresponding to the effective address (EA). The search is done regardless of the setting of Machine State Register (MSR) Instruction Relocate bit or the MSR Data Relocate bit. The search uses a portion of the EA including the least significant bits, and ignores the content of the Segment Registers. Entries that satisfy the search criteria are made invalid so will not be used to translate subsequent storage accesses.

The POWER instruction tlbi expands the EA to its virtual address and invalidates any information in the TLB for the virtual address, regardless of the setting of MSR Instruction Relocate bit or the MSR Data Relocate bit. The EA is placed into the general-purpose register (GPR) RA.

Consider the following when using the POWER instruction tlbi:

• If GPR RA is not 0, the EA is the sum of the contents of GPR RA and GPR RB. If GPR RA is 0, EA is the sum of the contents of GPR RB and 0.
• If GPR RA is not 0, EA is placed into GPR RA.
• If EA specifies an I/O address, the instruction is treated as a no-op, but if GPR RA is not 0, EA is placed into GPR RA.

The tlbie and tlbi instructions have one syntax form and do not affect the Fixed-Point Exception Register. If the Record bit (Rc) is set to 1, the instruction form is invalid.

Parameters

The following parameter pertains to the PowerPC instruction, tlbie, only:

The following parameters pertain to the POWER instruction, tlbi, only:

Security

The tlbie and tlbi instructions are privileged.

Related Information

Processing and Storage