sraw or sra (Shift Right Algebraic Word) Instruction

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AIX Version 4.3 Assembler Language Reference

sraw or sra (Shift Right Algebraic Word) Instruction

Purpose

Rotates the contents of a general-purpose register to the left by a specified number of bits, merges the rotated data with a word of 32 sign bits from that register under control of a generated mask, and places the result in another general-purpose register.

Syntax

PowerPC
sraw	RA,RS,RB
sraw.	RA,RS,RB

POWER
sra	RA,RS,RB
sra.	RA,RS,RB

Description

The sraw and sra instructions rotate the contents of the source general-purpose register (GPR) RS to the left by 32 minus N bits, where N is the shift amount specified in bits 27-31 of GPR RB, and merge the rotated word with a word of 32 sign bits from GPR RS under control of a generated mask. A word of 32 sign bits is generated by taking the sign bit of a GPR and repeating it 32 times to make a full word. This word can be either 0x0000 0000 or 0xFFFF FFFF depending on the value of the GPR.

The mask depends on the value of bit 26 in GPR RB.

Consider the following when using the sraw and sra instructions:

If bit 26 of GPR RB is zero, then a mask of N zeros followed by 32 minus N ones is generated.
If bit 26 of GPR RB is one, then a mask of all zeros is generated.

The merged word is placed in GPR RA. The sraw and sra instructions then AND the rotated data with the complement of the generated mask, OR the 32-bit result together, and AND the bit result with bit 0 of GPR RS to produce the Carry bit (CA).

The sraw and sra instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
sraw	None	CA	0	None
sraw.	None	CA	1	LT,GT,EQ,SO
sra	None	CA	0	None
sra.	None	CA	1	LT,GT,EQ,SO

The two syntax forms of the sraw instruction, and the two syntax forms of the sra instruction, always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instructions affect the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA	Specifies target general-purpose register where result of operation is stored.
RS	Specifies source general-purpose register for operation.
RB	Specifies source general-purpose register for operation.

Examples

The following code rotates the contents of GPR 4 to the left by 28 bits, merges the result with 32 sign bits under control of a generated mask, stores the result in GPR 6, and sets the Carry bit in the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0x9000 3000.
# Assume GPR 5 contains 0x0000 0024.
sraw 6,4,5
# GPR 6 now contains 0xFFFF FFFF.
```
The following code rotates the contents of GPR 4 to the left by 28 bits, merges the result with 32 sign bits under control of a generated mask, stores the result in GPR 6, and sets the Carry bit in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0xB004 3000.
# Assume GPR 5 contains 0x0000 0004.
sraw. 6,4,5
# GPR 6 now contains 0xFB00 4300.
# Condition Register Field 0 now contains 0x8.
```

Related Information

The addze or aze (Add to Zero Extended) instruction.

Fixed-Point Processor.

Fixed-Point Rotate and Shift Instructions.

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