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AIX Version 4.3 Assembler Language Reference

fmadd or fma (Floating Multiply-Add) Instruction

Purpose

Adds one floating-point operand to the result of multiplying two floating-point operands without an intermediate rounding operation.

Syntax

PowerPC
fmadd FRT,FRA,FRC,FRB
fmadd. FRT,FRA,FRC,FRB
POWER
fma FRT,FRA,FRC,FRB
fma. FRT,FRA,FRC,FRB

PowerPC
fmadds FRT,FRA,FRC,FRB
fmadds. FRT,FRA,FRC,FRB

Description

The fmadd and fma instructions multiply the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRA by the 64-bit, double-precision floating-point operand in FPR FRC, and then add the result of this operation to the 64-bit, double-precision floating-point operand in FPR FRB.

The fmadds instruction multiplies the 32-bit, single-precision floating-point operand in FPR FRA by the 32-bit, single-precision floating-point operand in FPR FRC and adds the result of this operation to the 32-bit, single-precision floating-point operand in FPR FRB.

The result is rounded under control of the Floating-Point Rounding Control Field RN of the Floating-Point Status and Control Register and is placed in the target FPR FRT.

Note: If an operand is a denormalized number, then it is prenormalized before the operation is begun.

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation Exceptions, when the Floating-Point Invalid Operation Exception Enable bit is 1.

The fmadd, fmadds, and fm instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

Syntax Form Floating-Point Status and Control Register Record Bit (Rc) Condition Register Field 1
fmadd C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None
fmadd. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX
fmadds C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None
fmadds. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX
fma C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 0 None
fma. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI,VXIMZ 1 FX,FEX,VX,OX

All syntax forms of the fmadd, fmadds, and fm instructions always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Parameters

FRT Specifies target floating-point register for operation.
FRA Specifies source floating-point register containing a multiplier.
FRB Specifies source floating-point register containing the addend.
FRC Specifies source floating-point register containing a multiplier.

Examples

  1. The following code multiplies the contents of FPR 4 and FPR 5, adds the contents of FPR 7, places the result in FPR 6, and sets the Floating-Point Status and Control Register to reflect the result of the operation: 
    # Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPR 7 contains 0x3DE2 6AB4 B33C 110A.
# Assume FPSCR = 0.
fmadd 6,4,5,7
# FPR 6 now contains 0xC070 D7FF FFFF F6CB.
# FPSCR now contains 0x8206 8000.
  2. The following code multiplies the contents of FPR 4 and FPR 5, adds the contents of FPR 7, places the result in FPR 6, and sets the Floating-Point Status and Control Register and Condition Register Field 1 to reflect the result of the operation: 
    # Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPR 7 contains 0x3DE2 6AB4 B33C 110A.
# Assume FPSCR = 0 and CR = 0.
fmadd. 6,4,5,7
# FPR 6 now contains 0xC070 D7FF FFFF F6CB.
# FPSCR now contains 0x8206 8000.
# CR now contains 0x0800 0000.

Related Information

Floating-Point Processor.

Interpreting the Contents of a Floating-Point Register.

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