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Understanding the Diagnostic Subsystem for AIX

PCI Configuration Space for I/O Devices

There are several writable fields in the standard PCI Configuration Header for PCI devices. They are:

Some of these are written by the firmware and should never be changed by the device driver. The PCI Configuration Header Programming Table must be followed when programming the PCI Configuration Header registers.

PCI Configuration Header Programming Table

Register/Bit Name Firmware Action
(Boot or ibm, configure-connector call)
Software (Device Driver) Action
Command/Fast Back-to-Back Enable Write to a value of 0 on platforms capable of PCI Hot Plug. May be written to a value of 1 on non-Hot-Plug capable platforms if all I/O devices on the same PCI bus are capable of Fast Back-to-Back transfers. Preserve value
Command/SERR# enable Write a value of 1
Command/Wait cycle control Write to a value of 0 (may be hardwired to a 1, so may be a 1 when read even after being written to a 0)
Command/Parity Error Response Write a value of 1
Command/VGA Palette snoop Write a value of 0
Command/Memory Write and Invalidate Enable Write to 0 (reset value)
Command/Special Cycles
Command/Bus Master Write to 0 (reset value) unless boot device. Must write to a 1 before the first DMA operation. Must write to a 0 before unconfiguring device driver.
Command/Memory Space Write a value of 0 (reset value) unless boot device, in which case does not write a value of 1 until BARs and Expansion ROM Base Address are set. Only written to a 1 if that specific address space is used for that I/O device. Must write to a 1 before the first operation (if any) to the I/O devices memory space. Must write to a 0 before unconfiguring device driver.
Command/IO Space Must write to a 1 before the first operation (if any) to the I/O devices I/O space. Must write to a 0 before unconfiguring device driver.
Build-in Self Test (BIST) Write a value of 0 If BIST is implemented, can write to a 1 to initiate BIST
Latency Timer Initialize to a system-specific value Preserve value
Cache Line Size
Base Address Registers Initialize based on size requested and address space available Writes based on the ODM M.n and O.n customized attributes
Expansion ROM Base Address Writes based on the ODM M.n and O.n customized attributes. Write LSB to a 0 before enabling the Command/Memory Space if Expansion ROM not used by software.
Interrupt Line Ignore Ignore - get information from ODM

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