Create dependencies in makefiles.
makedepend [ -DName=Def] [ -DName] [ -IIncludeDir ] [ -YIncludeDir ] [ -a ] [ -fMakeFile ] [ -oObjSuffix ] [ -pObjPrefix ] [ -sString ] [ -wWidth ] [ -v] [ -m ] [ --Options-- ] SourceFile ...
The makedepend command reads each SourceFile in sequence and parses it like a C-preprocessor. It processes all #include, #define, #undef, #ifdef, #ifndef, #endif, #if, and #else directives to determine which #include directives need to be used in a compilation. Any #include directives can reference files having other #include directives, and parsing occurs in these files as well.
Every file that a SourceFile includes, directly or indirectly, is what makedepend calls a "dependency." These dependencies are then written to a makefile in such a way that the make command can determine which object files must be recompiled when a dependency has changed.
By default, makedepend places its output in the file named makefile if it exists, otherwise Makefile. An alternate makefile may be specified with the -f flag. makedepend first searches the available makefile for the line:
# DO NOT DELETE THIS LINE - make depend depends on it.
or one provided with the -s flag, as a delimiter for the dependency output. If it finds the line, it deletes everything following the line to the end of the makefile and puts the output after the line. If makedepend does not find the line, it appends the delimited string to the end of the makefile and places the output immediately after the string.
For each SourceFile appearing on the command line, makedepend puts lines in the makefile in the following form.
SourceFile.o: dfile ...
Where SourceFile.o is the name from the command line with its suffix replaced with .o, and dfile is a dependency discovered in an #include directive while parsing the SourceFile or one of the files it included.
The algorithm used in this command assumes that all files compiled by a single makefile will be compiled with roughly the same -I and -D flags, and that most files in a single directory will include largely the same files.
Given these assumptions, makedepend expects to be called once for each makefile, with all source files that are maintained by the make file appearing on the command line. It parses each source and include file only once, maintaining an internal symbol table for each. As a result, the first file on the command line takes an amount of time proportional to the amount of time that a normal C preprocessor takes. On subsequent files, if it encounters an include file that it has already parsed, it does not parse again.
For example, imagine you are compiling two files, file1.c and file2.c, each includes the header file header.h. The header.h file includes the files def1.h and def2.h. When you run the command:
makedepend file1.c file2.c
then makedepend will first parse file1.c and consequently, header.h and then def1.h and def2.h. It then decides that the dependencies for this first file are:
file1.o: header.h def1.h def2.h
But when the program parses the second file, file2.c and discovers that it, too, includes header.h, it does not parse the file, but simply adds header.h, def1.h and def2.h to the list of dependencies for file2.o.
Note: If you do not have the source for cpp (the Berkeley C preprocessor), then makedepend will compile in such a way that all #if directives will evaluate to False, regardless of their actual value. This may cause the wrong #include directives to be evaluated. In these cases, it is recommended that you write a new parser for #if expressions. The need for a new parser should be clear from the following example:Imagine you are parsing two files file1.c and file2.c, each includes the file def.h. The list of files that def.h includes might be very different when def.h is included by file1.c than when it is included by file2.c. But once makedepend arrives at a list of dependencies for a file, it is cast in concrete.
Note: The makedepend command ignores flags it does not understand. Flag usage is similar to that of the cc command.
Normally, makedepend will be used in a makefile target so that typing makedepend updates the dependencies for the makefile.
SRCS=file1.c file2.c ...
CFLAGS=-O -DHACK -I../foobar -xyz
depend:
makedepend -- $(CFLAGS) -- $(SRCS)
The cc command, make command.