tlbld (Load Data TLB Entry) Instruction

Purpose

Loads the data Translation Look-Aside Buffer (TLB) entry to assist a TLB reload function performed in software on the PowerPC 603 RISC Microprocessor.

Notes:

1. The tlbld instruction is supported only on the PowerPC 603 RISC Microprocessor. It is not part of the PowerPC architecture and not part of the POWER architecture.
2. TLB reload is usually done by the hardware, but on the PowerPC 603 RISC Microprocessor this is done by software.
3. When AIX Version 4 is installed on a system using the PowerPC 603 RISC Microprocessor, software to perform the TLB reload function is provided as part of the operating system. You are likely to need to use this instruction only if you are writing software for the PowerPC 603 RISC Microprocessor intended to operate without AIX Version 4.

Syntax

PowerPC 603 RISC Microprocessor

Description

For better understanding, the following information is presented:

• Information about a typical TLB reload function that would call the tlbld instruction.
• An explanation of what the tlbld instruction does.

Typical TLB Reload Function

In the processing of the address translation, the Effective Address (EA) is first translated into a Virtual Address (VA). The part of the Virtual Address is used to select the TLB entry. If an entry is not found in the TLB, a miss is detected. When a miss is detected, the EA is loaded into the data TLB Miss Address (DMISS) register. The first word of the target Page Table Entry is loaded into the data TLB Miss Compare (DCMP) register. A routine is invoked to compare the content of DCMP with all the entries in the primary Page Table Entry Group (PTEG) pointed to by the HASH1 register and all the entries in the secondary PTEG pointed to by the HASH2 register. When there is a match, the tlbld instruction is invoked.

tlbld Instruction Function

The tlbld instruction loads the data Translation Look-Aside Buffer (TLB) entry selected by the content of register RB in the following way:

• The content of the data TLB Miss Compare (DCMP) register is loaded into the higher word of the data TLB entry.
• The contents of the RPA register and the data TLB Miss Address (DMISS) register are merged and loaded into the lower word of the data TLB entry.

The tlbld instruction has one syntax form and does not affect the Fixed-Point Exception Register. If the Record bit (Rc) is set to 1, the instruction form is invalid.

Parameters

Security

The tlbld instruction is privileged.

Related Information

The tlbli (Load Instruction TLB Entry) Instruction.

Sections 2.4, 4.11.4, 7.5.2, 7.6.1, and 7.6.3 of PowerPC 603 RISC Microprocessor User's Manual.

Section 12.5 of PowerPC Architecture.