Stores in memory two double-precision values at two consecutive doubleword locations and updates the address base.
Note: The stfqu instruction is supported only in the POWER2 implementation of the POWER architecture.
The stfqu instruction stores in memory the contents of two consecutive floating-point registers (FPR) at the location specified by the effective address (EA).
DS is sign-extended to 30 bits and concatenated on the right with b'00' to form the offset value. If general-purpose register (GPR) RA is 0, the offset value is the EA. If GPR RA is not 0, the offset value is added to GPR RA to generate the EA. The contents of FPR FRS is stored into the doubleword of storage at the EA. If FPR FRS is 31, then the contents of FPR 0 is stored into the doubleword at EA+8; otherwise, the contents of FRS+1 is stored into the doubleword at EA+8.
If GPR RA is not 0, the EA is placed into GPR RA.
The stfqu instruction has one syntax form and does not affect the Floating-Point Status and Control Register or Condition Register Field 0.
|FRS||Specifies the first of two floating-point registers that contain the values to be stored.|
|DS||Specifies a 14-bit field used as an immediate value for the EA calculation.|
|RA||Specifies one source general-purpose register for the EA calculation and the target register for the EA update.|
The lfqux (Load Floating-Point Quad with Update Indexed) instruction.
Floating-Point Load and Store Instructions.