stfiwx (Store Floating-Point as Integer Word Indexed)

Purpose

Stores the low-order 32 bits from a specified floating point register in a specified word location in memory.

Note: The stfiwx instruction is defined only in the PowerPC architecture and is an optional instruction. It is supported on the PowerPC 603 RISC Microprocessor and the PowerPC 604 RISC Microprocessor, but not on the PowerPC 601 RISC Microprocessor.

Syntax

Description

The stfifx instruction stores the contents of the low-order 32 bits of floating-point register (FPR) FRS,without conversion, into the word storage addressed by the effective address (EA).

If general-purpose register (GPR) RA is not 0, the EA is the sum of the contents of GPRs RA and RB. If GPR RA is 0, then the EA is the contents of GPR RB.

The stfiwx instruction has one syntax form and does not affect the Floating-Point Status and Control Register or Condition Register Field 0.

If the contents of register FRS was produced, either directly or indirectly by a Load Floating Point Single Instruction, a single-precision arithmetic instruction, or the frsp (Floating Round to Single Precision) instruction, then the value stored is undefined. (The contents of FRS is produced directly by such an instruction if FRS is the target register of such an instruction. The contents of register FRS is produced indirectly by such an instruction if FRS is the final target register of a sequence of one or more Floating Point Move Instructions, and the input of the sequence was produced directly by such an instruction.)

Parameters

Examples

The following code stores the contents of FPR 6 into a location in memory addressed by GPR 5 and GPR 4:

.csect data[rw]
buffer: .long 0,0,0,0
# Assume FPR 6 contains 0x4865 6C6C 6F20 776F.
# Assume GPR 4 contains 0x0000 0008.
# Assume GPR 5 contains the address of buffer.
.csect text[pr]
stfiwx 6,4,5
# 6F20 776F is now stored at the
# address buffer+8.

Related Information

Floating-Point Processor.

Floating-Point Load and Store Instructions.