rac (Real Address Compute) Instruction

Purpose

Translates an effective address into a real address and stores the result in a general-purpose register.

Note: The rac instruction is supported only in the POWER architecture.

Syntax

Description

The rac instruction computes an effective address (EA) from the sum of the contents of general-purpose register (GPR) RA and the contents of GPR RB, and expands the EA into a virtual address.

If RA is not 0 and if RA is not RT, then the rac instruction stores the EA in GPR RA, translates the result into a real address, and stores the real address in GPR RT.

Consider the following when using the rac instruction:

• If GPR RA is 0, then EA is the sum of the contents of GPR RB and 0.
• EA is expanded into its virtual address and translated into a real address, regardless of whether data translation is enabled.
• If the translation is successful, the EQ bit in the condition register is set and the real address is placed in GPR RT.
• If the translation is unsuccessful, the EQ bit is set to 0, and 0 is placed in GPR RT.
• If the effective address specifies an I/O address, the EQ bit is set to 0, and 0 is placed in GPR RT.
• The reference bit is set if the real address is not in the Translation Look-Aside buffer (TLB).

The rac instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

The two syntax forms of the rac instruction do not affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction effects the Equal (EQ) and Summary Overflow (SO) bit in Condition Register Field 0.

Note: The hardware may first search the Translation Look-Aside buffer for the address. If this fails, the Page Frame table must be searched. In this case, it is not necessary to load a Translation Look-Aside buffer entry.

Parameters

Security

The rac instruction instruction is privileged.

Related Information

Processing and Storage